Bizarre Patents
Combination Beverage Container and Spittoon
A combination beverage container and spittoon includes a bottom portion including outer wall and a first inner wall defining a spittoon space.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Application No. | Application Title | Issue Date |
| 20120131283 | MEMORY MANAGER FOR A NETWORK COMMUNICATIONS PROCESSOR ARCHITECTURE Described embodiments provide a network processor having a plurality of processing modules coupled to a system cache and a shared memory. A memory manager allocates blocks of the shared memory to a requesting one of the processing modules. The allocated blocks store dat... | 05/24/2012 |
| 20120084516 | METHODS AND APPARATUSES FOR DATA RESOURCE PROVISION Methods and apparatuses are provided for data resource provision. A method may include receiving a request for a first data resource. The request may include an indication of an additional data resource that may be requested in a future request. The method may further i... | 04/05/2012 |
| 20110320740 | METHOD FOR OPTIMIZING SEQUENTIAL DATA FETCHES IN A COMPUTER SYSTEM A computer implemented method of optimizing sequential data fetches in a computer system is provided. The method includes fetching a data segment from a main memory, the data segment having a plurality of target data entries; extracting a first portion of the data segme... | 12/29/2011 |
| 20110289257 | METHOD AND APPARATUS FOR ACCESSING CACHE MEMORY A request for reading data from a memory location of a main memory is received, the memory location being identified by a physical memory address. In response to the request, a cache memory is accessed based on the physical memory address to determine whether the cache ... | 11/24/2011 |
| 20110289279 | DATA CACHING IN A NETWORK COMMUNICATIONS PROCESSOR ARCHITECTURE Described embodiments provide a method of coherently storing data in a network processor having a plurality of processing modules and a shared memory. A control processor sends an atomic update request to a configuration controller. The atomic update request corresponds... | 11/24/2011 |
| 20110289278 | METHOD OF ESTIMATING READ LEVEL FOR A MEMORY DEVICE, MEMORY CONTROLLER THEREFOR, AND RECORDING MEDIUM A method of estimating a read level for a memory device includes calculating first information corresponding to at least one among information about the number of cells having a particular logic level in data to be programmed and information about the number of cells ha... | 11/24/2011 |
| 20110264866 | TECHNIQUE FOR USING MEMORY ATTRIBUTES A technique for using memory attributes to relay information to a program or other agent. More particularly, embodiments of the invention relate to using memory attribute bits to check various memory properties in an efficient manner.... | 10/27/2011 |
| 20110208907 | Protected Cache Architecture And Secure Programming Paradigm To Protect Applications Embodiments of the present invention provide a secure programming paradigm, and a protected cache that enable a processor to handle secret/private information while preventing, at the hardware level, malicious applications from accessing this information by circumventin... | 08/25/2011 |
| 20110191546 | MEMORY ACCESS PREDICTION An apparatus for memory access prediction which includes a plurality of processors, a plurality of memory caches associated with the processors, a plurality of saturation counters associated with the processors, each of the saturation counters having an indicator bit, a... | 08/04/2011 |
| 20110161590 | SYNCHRONIZING ACCESS TO DATA IN SHARED MEMORY VIA UPPER LEVEL CACHE QUEUING A processing unit includes a store-in lower level cache having reservation logic that determines presence or absence of a reservation and a processor core including a store-through upper level cache, an instruction execution unit, a load unit that, responsive to a hit i... | 06/30/2011 |
| 20110161585 | PROCESSING NON-OWNERSHIP LOAD REQUESTS HITTING MODIFIED LINE IN CACHE OF A DIFFERENT PROCESSOR Methods and apparatus to efficiently process non-ownership load requests hitting modified line (M-line) in cache of a different processor are described. In one embodiment, a first agent changes the state of a first data and forwards it to a second, requesting agent who ... | 06/30/2011 |
| 20110131382 | Extract Cache Attribute Facility and Instruction Therefore A facility and cache machine instruction of a computer architecture for specifying a target cache cache-level and a target cache attribute of interest for obtaining a cache attribute of one or more target caches. The requested cache attribute of the target cache(s) is s... | 06/02/2011 |
| 20110119451 | NON-BLOCKING DATA TRANSFER VIA MEMORY CACHE MANIPULATION A cache controller in a computer system is configured to manage a cache such that the use of bus bandwidth is reduced. The cache controller receives commands from a processor. In response, a cache mapping maintaining information for each block in the cache is modified. ... | 05/19/2011 |
| 20110107034 | CACHE DEVICE A cache device comprises: data memory that includes a plurality of ways for storing a part of data of a main memory; tag memory that includes a plurality of ways, each of which is for storing tag contained in address of data recorded in each way of the data memory; comp... | 05/05/2011 |
| 20110022773 | Fine Grained Cache Allocation A mechanism is provided in a virtual machine monitor for fine grained cache allocation in a shared cache. The mechanism partitions a cache tag into a most significant bit (MSB) portion and a least significant bit (LSB) portion. The MSB portion of the tags is shared amon... | 01/27/2011 |
| 20100332766 | SUPPORTING EFFICIENT SPIN-LOCKS AND OTHER TYPES OF SYNCHRONIZATION IN A CACHE-COHERENT MULTIPROCESSOR SYSTEM Some embodiments of the present invention provide a system that acquires a lock in a shared memory multiprocessor system. During operation, the system loads the lock into a cache associated with the thread and then reads a value of the lock. If the value indicates that ... | 12/30/2010 |
| 20100333093 | FACILITATING TRANSACTIONAL EXECUTION THROUGH FEEDBACK ABOUT MISSPECULATION One embodiment provides a system that facilitates the execution of a transaction for a program in a hardware-supported transactional memory system. During operation, the system records a misspeculation indicator of the transaction during execution of the transaction usi... | 12/30/2010 |
| 20100318747 | ATOMIC MEMORY OPERATION CACHE PROTOCOL WITH OPPORTUNISTIC COMBINING An atomic memory operation cache comprises a cache memory operable to cache atomic memory operation data, a write timer, and a cache controller. The cache controller is operable to update main memory with one or more dirty atomic memory operation cache entries stored in... | 12/16/2010 |
| 20100306478 | DATA CACHE WITH MODIFIED BIT ARRAY A microprocessor includes first and second functional units and a data cache having a data array having a write port, a modified bit array having a read port and a write port, and a tag array having a read port, each array having the corresponding predetermined organiza... | 12/02/2010 |
| 20100287340 | Concurrent Execution of Critical Sections by Eliding Ownership of Locks One embodiment of the present invention provides a system that facilitates avoiding locks by speculatively executing critical sections of code. During operation, the system allows a process to speculatively execute a critical section of code within a program without fir... | 11/11/2010 |
| 20100257320 | Cache Replacement Policy Techniques for replacing one or more blocks in a cache, the one or more blocks being associated with a plurality of data streams, are provided. The one or more blocks in the cache are grouped into one or more groups. Each group corresponding to one of the plurality of d... | 10/07/2010 |
| 20100241814 | BANDWIDTH-EFFICIENT DIRECTORY-BASED COHERENCE PROTOCOL Some embodiments of the present invention provide a system that processes a request for a cache line in a multiprocessor system that supports a directory-based cache-coherence scheme. During operation, the system receives the request for the cache line from a requesting... | 09/23/2010 |
| 20100241813 | Data subscribe-and-publish mechanisms and methods for producer-consumer pre-fetch communications A system supporting producer-consumer pre-fetch communications includes a first processor, wherein the first processor is a producer node, and a second processor, wherein the second processor is a consumer node. The system further includes a data subscribe mechanism for... | 09/23/2010 |
| 20100235586 | MULTI-CORE PROCESSOR SNOOP FILTERING Systems, methods, and devices for reducing snoop traffic in a central processing unit are provided. In accordance with one embodiment, an electronic device includes a central processing unit having a plurality of cores. A cache memory management system may be associated... | 09/16/2010 |
| 20100185904 | System and Method for Fast Cache-Hit Detection A system and method for fast detection of cache memory hits in memory systems with error correction/detection capability is provided. A circuit for determining an in-cache status of a memory address comprises an error detect unit coupled to a cache memory, a comparison ... | 07/22/2010 |
| 20100169619 | Efficient Encoding for Detecting Load Dependency on Store with Misalignment In one embodiment, an apparatus comprises a queue comprising a plurality of entries and a control unit coupled to the queue. The control unit is configured to allocate a first queue entry to a store memory operation, and is configured to write a first even offset, a fir... | 07/01/2010 |
| 20100153657 | OPERATION OF AN INPUT/OUTPUT LINK Included are embodiments for facilitating operation of an input/output (I/O) link. At least one embodiment of a method includes receiving a first cache line from a memory controller and determining whether the first cache line corresponds to a first portion of data. Som... | 06/17/2010 |
| 20100138614 | Compression Status Bit Cache And Backing Store One embodiment of the present invention sets forth a technique for increasing available storage space within compressed blocks of memory attached to data processing chips, without requiring a proportional increase in on-chip compression status bits. A compression status... | 06/03/2010 |
| 20100131718 | MULTIPROCESSOR SYSTEM A multiprocessor system includes cache systems arranged in correspondence with processor cores, and each including a cache memory which stores a cache line, a shared memory shared by the processor cores, and an arbiter configured to arbitrate access requests sent from t... | 05/27/2010 |
| 20100122038 | METHODS AND APPARATUSES FOR IMPROVING SPECULATION SUCCESS IN PROCESSORS Methods and apparatuses are disclosed that allow for improved speculation success in execute ahead microprocessors. In some embodiments, the method may include speculatively executing a first thread of a program code while a second thread of the program code is executin... | 05/13/2010 |
| 20100115207 | METHOD AND SYSTEM FOR IMPLEMENTING MULTIUSER CACHED PARAMETERIZED CELLS An improved approach to pcell caching is disclosed that enables safe and efficient multi-user access to pcell caches. Locking structures are used in conjunction with counters to provide multi-user support for pcell caches. When a modification occurs to cached pcell data... | 05/06/2010 |
| 20100106915 | POLL BASED CACHE EVENT NOTIFICATIONS IN A DISTRIBUTED CACHE Systems and methods that supply poll based notification system in a distributed cache, for tracking changes to cache items. Local caches on the client can employ the notification system to keep the local objects in sync with the backend cache service; and can further dy... | 04/29/2010 |
| 20100095071 | Cache control apparatus and cache control method A cache control apparatus includes a plurality of processing units, each performing, in a mutually independent manner, corresponding processing that constitutes a pipeline process of outputting cache data with respect to requests belonging to threads, holding units, eac... | 04/15/2010 |
| 20100088550 | CACHE MEMORY APPARATUS, EXECUTION PROCESSING APPARATUS AND CONTROL METHOD THEREOF A cache memory apparatus is configured to include a data holding unit comprising a plurality of ways that has a plurality of cache lines; an alternation data register to hold data in one line of the cache lines or in a part of the cache lines; an alternation address reg... | 04/08/2010 |
| 20100057996 | CACHE LOGIC VERIFICATION APPARATUS AND CACHE LOGIC VERIFICATION METHOD A cache logic verification apparatus is provided. The cache logic verification apparatus includes an acquisition unit that acquires an ongoing process in each stage of a stepped operation to judge whether data to be read in a cache memory holding a copy of contents of a... | 03/04/2010 |
| 20090327615 | Access Speculation Predictor with Predictions Based on a Scope Predictor An access speculation predictor may predict whether to perform speculative retrieval of data for a data request from a main memory based on whether a scope predictor indicates whether a local or global request is predicted to be necessary to obtain the data for the data... | 12/31/2009 |
| 20090300294 | UTILIZATION OF A STORE BUFFER FOR ERROR RECOVERY ON A STORE ALLOCATION CACHE MISS A processor and cache is coupled to a system memory via a system interconnect. A first buffer circuit coupled to the cache receives one or more data words and stores the one or more data words in each of one or more entries. The one or more data words of a first entry a... | 12/03/2009 |
| 20090292883 | Apparatus, Method, and Computer Program Product for Memory Validation Operations in a Memory In accordance with an example embodiment of the present invention, an apparatus, comprising a first memory, wherein the first memory is configured to store data related to a first event, store a memory validation indicator related to a second event, and a second memory,... | 11/26/2009 |
| 20090238005 | MULTI-PLANE TYPE FLASH MEMORY AND METHODS OF CONTROLLING PROGRAM AND READ OPERATIONS THEREOF A multi-plane type flash memory device comprises a plurality of planes each including a plurality of memory cell blocks, page buffers each latching an input data bit to be output to its corresponding plane or latching an output data bit to be received from the correspon... | 09/24/2009 |
| 20090193199 | Method for Increasing Cache Directory Associativity Classes Via Efficient Tag Bit Reclaimation In a method of generating a cache directory to include a plurality of associativity classes, each associativity class includes an address tag including a plurality of address bits. Each address tag is configured to store a unique address to a specific location in an mem... | 07/30/2009 |
