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| Application No. | Application Title | Issue Date |
| 20120131281 | Converting Victim Writeback to a Fill In one embodiment, a processor may be configured to write ECC granular stores into the data cache, while non-ECC granular stores may be merged with cache data in a memory request buffer. In one embodiment, a processor may be configured to detect that a victim block writ... | 05/24/2012 |
| 20120072470 | WRITE BEHIND CACHE WITH M-TO-N REFERENTIAL INTEGRITY A batch of data records generated by at least one application for persistent storage is cached by a cache management device. At least one of the batch of data records includes at least one foreign key reference that each references one non-existent data record. It is de... | 03/22/2012 |
| 20120042133 | MULTI-CORE PROCESSOR SYSTEM AND MULTI-CORE PROCESSOR According to one embodiment, a state manager classifies an area allocated to the multi-core processor in a first memory area into one of a first state in which allocation to processor cores is not performed, a second state in which allocation to one of the processor cor... | 02/16/2012 |
| 20110320730 | NON-BLOCKING DATA MOVE DESIGN A mechanism for data buffering is provided. A portion of a cache is allocated as buffer regions, and another portion of the cache is designated as random access memory (RAM). One of the buffer regions is assigned to a processor. A data block is stored to the one of the ... | 12/29/2011 |
| 20110276763 | MEMORY BUS WRITE PRIORITIZATION A data processing system includes a multi-level cache hierarchy including a lowest level cache, a processor core coupled to the multi-level cache hierarchy, and a memory controller coupled to the lowest level cache and to a memory bus of a system memory. The memory cont... | 11/10/2011 |
| 20110276762 | COORDINATED WRITEBACK OF DIRTY CACHELINES A data processing system includes a processor core and a cache memory hierarchy coupled to the processor core. The cache memory hierarchy includes at least one upper level cache and a lowest level cache. A memory controller is coupled to the lowest level cache and to a ... | 11/10/2011 |
| 20110246723 | CACHE MANAGEMENT POLICY AND CORRESPONDING DEVICE A cache management policy is provided, comprising a method for writing back to a memory (104) a data element set (122) stored in a cache (110). The method reduces the time some items stay in the cache, and thereby improves the utilization of the cac... | 10/06/2011 |
| 20110213933 | INFORMATION PROCESSING APPARATUS AND MEMORY CONTROL APPARATUS A memory control apparatus, in a case of receiving from a processor, under a condition where the number of cache memories retaining a copy of data stored in a main storage device is one, a notification to the effect that data retained in the cache memory is purged, upda... | 09/01/2011 |
| 20110191543 | Area and power efficient data coherency maintenance An apparatus for storing data that is being processed is disclosed. The apparatus comprises: a cache associated with a processor and for storing a local copy of data items stored in a memory for use by the processor, monitoring circuitry associated with the cache for mo... | 08/04/2011 |
| 20110167224 | CACHE MEMORY, MEMORY SYSTEM, DATA COPYING METHOD, AND DATA REWRITING METHOD A cache memory according to an aspect of the present invention including entries each of which includes a tag address, line data, and a dirty flag, the cache memory includes: a command execution unit which rewrites, when a first command is instructed by a processor, a t... | 07/07/2011 |
| 20110161585 | PROCESSING NON-OWNERSHIP LOAD REQUESTS HITTING MODIFIED LINE IN CACHE OF A DIFFERENT PROCESSOR Methods and apparatus to efficiently process non-ownership load requests hitting modified line (M-line) in cache of a different processor are described. In one embodiment, a first agent changes the state of a first data and forwards it to a second, requesting agent who ... | 06/30/2011 |
| 20110153944 | Secure Cache Memory Architecture A variety of circuits, methods and devices are implemented for secure storage of sensitive data in a computing system. A first dataset that is stored in main memory is accessed and a cache memory is configured to maintain logical consistency between the main memory and ... | 06/23/2011 |
| 20110131379 | PROCESSOR AND METHOD FOR WRITEBACK BUFFER REUSE A processor may include a writeback configured to perform a first writeback operation to store corresponding writeback data back to a lower-level memory upon eviction of the writeback data, and a writeback buffer configured to store the writeback data after the writebac... | 06/02/2011 |
| 20110125968 | ARCHITECTURE AND METHOD FOR CACHE-BASED CHECKPOINTING AND ROLLBACK A cache system to compare memory transactions while facilitating checkpointing and rollback is provided. The system includes at least one processor core including at least one cache operating in write-through mode, at least two checkpoint caches operating in write-back ... | 05/26/2011 |
| 20110125972 | INFORMATION RECORDING DEVICE AND INFORMATION RECORDING METHOD In one embodiment, there is provided an information recording device that includes: a plurality of cache buffers on which writing is performed in response to an external write request; and a controller configured to determine, according to an LRU algorithm, which of the... | 05/26/2011 |
| 20110113260 | Block Encryption Security for Integrated Microcontroller and External Memory System A secure microcontroller system comprising an integrated cache sub-system, crypto-engine, buffer sub-system and external memory is described according to various embodiments of the invention. The secure microcontroller incorporates block encryption methods to ensure tha... | 05/12/2011 |
| 20110113202 | CACHE FLUSH BASED ON IDLE PREDICTION AND PROBE ACTIVITY LEVEL A processing node tracks probe activity level associated with its cache. The processing node and/or processing system further predicts an idle duration. If the probe activity level increases above a threshold probe activity level, and the idle duration prediction is abo... | 05/12/2011 |
| 20110113199 | PREFETCH OPTIMIZATION IN SHARED RESOURCE MULTI-CORE SYSTEMS An apparatus and method is described herein for optimization to prefetch throttling, which potentially enhances performance, reduces power consumption, and maintains positive gain for workloads that benefit from prefetching. More specifically, the optimizations describe... | 05/12/2011 |
| 20110099337 | PROCESSING CIRCUIT WITH CACHE CIRCUIT AND DETECTION OF RUNS OF UPDATED ADDRESSES IN CACHE LINES A circuit that comprises a processor core (100), a background memory (12) and a cache circuit (102) between the processor core (100) and the background memory (12). In operation a sub-range of a plurality of successive addresses is det... | 04/28/2011 |
| 20110099336 | CACHE MEMORY CONTROL CIRCUIT AND CACHE MEMORY CONTROL METHOD A cache memory control circuit has a plurality of counters, each of which is provided per set and per memory space and configured to count how many pieces of data of a corresponding memory space is stored in a corresponding set. The cache memory control circuit controls... | 04/28/2011 |
| 20110093646 | PROCESSOR-BUS ATTACHED FLASH MAIN-MEMORY MODULE A method for processing a read request identifying an address. The method includes receiving, at a module including a flash memory and a memory buffer, the read request from a requesting processor, mapping, using a coherence directory controller within the module, the a... | 04/21/2011 |
| 20110093661 | MULTIPROCESSOR SYSTEM WITH MIXED SOFTWARE HARDWARE CONTROLLED CACHE MANAGEMENT A multiprocessor system has a background memory and a plurality of processing elements (10), each comprising a processor core (100) and a cache circuit (102). The processor cores (100) execute programs of instructions and the cache circuits (... | 04/21/2011 |
| 20110078384 | MEMORY MIRRORING AND MIGRATION AT HOME AGENT Methods and apparatus relating to memory mirroring and migration at a Home Agent (HA) are described. In one embodiment, a home agent may mirror its data at a slave agent. In some embodiments, a bit in a directory may indicate status of cache lines. Other embodiments are... | 03/31/2011 |
| 20110047333 | ALLOCATING PROCESSOR CORES WITH CACHE MEMORY ASSOCIATIVITY Techniques are generally described related to a multi-core processor with a plurality of processor cores and a cache memory shared by at least some of the processor cores. The multi-core processor can be configured for separately allocating a respective level of cache m... | 02/24/2011 |
| 20110047335 | MULTIPROCESSOR, CACHE SYNCHRONIZATION CONTROL METHOD AND PROGRAM THEREFOR There is provided a cache synchronization control method by which contents of a plurality of caches can be synchronized without a programmer explicitly setting a synchronization point, and the contents of the caches can be synchronized without scanning all cache blocks.... | 02/24/2011 |
| 20110047336 | Converting Victim Writeback to a Fill In one embodiment, a processor may be configured to write ECC granular stores into the data cache, while non-ECC granular stores may be merged with cache data in a memory request buffer. In one embodiment, a processor may be configured to detect that a victim block writ... | 02/24/2011 |
| 20100325367 | Write-Back Coherency Data Cache for Resolving Read/Write Conflicts A write-back coherency data cache for temporarily holding cache lines. Upon receiving a processor request for data, a determination is made from a coherency directory whether a copy of the data is cached in a write-back cache located in a memory controller hardware. The... | 12/23/2010 |
| 20100306448 | CACHE AUTO-FLUSH IN A SOLID STATE MEMORY DEVICE A device, system and method in which data in a write cache, that must at some point be written to non-volatile memory, is written to non-volatile memory after expiration of a threshold time period during which no new host commands are received. If either the last dirty ... | 12/02/2010 |
| 20100281222 | CACHE SYSTEM AND CONTROLLING METHOD THEREOF A cache system and a method for controlling the cache system are provided. The cache system includes a plurality of caches, a buffer module, and a migration selector. Each of the caches is accessed by a corresponding processor. Each of the caches includes a plurality of... | 11/04/2010 |
| 20100262771 | DATA STORAGE SYSTEM AND CACHE DATA-CONSISTENCY ASSURANCE METHOD According to one embodiment, a data storage system includes a controller which accesses a first storage device using a first module on startup and accesses the first storage device using a second module after the startup. The first module records, when the write-target ... | 10/14/2010 |
| 20100211746 | CACHE DEVICE A cache device interposed between a processor and a memory device, including: a cache memory storing data from the memory device; a buffer holding output data output from the processor; a control circuit determining, on the basis of a request to access the memory device... | 08/19/2010 |
| 20100174871 | INPUT/OUTPUT CONTROL SYSTEM, INPUT/OUTPUT CONTROL METHOD AND INPUT/OUTPUT CONTROL PROGRAM An input/output control system of an information processing apparatus that includes a first storage area and a second storage area and carries out an input/output processing using a part or whole of the first storage area as a cache. The input/output control system incl... | 07/08/2010 |
| 20100174870 | SYSTEM AND METHOD TO PRESERVE AND RECOVER UNWRITTEN DATA PRESENT IN DATA CACHE OF A DISK SUBSYSTEM ACROSS POWER OUTAGES Disclosed are a system and method to preserve and recover unwritten data present in data cache of a disk subsystem across power outages. In one embodiment, a method of a controller is described. The method includes applying a write-back technique between a host server a... | 07/08/2010 |
| 20100153654 | DATA PROCESSING METHOD AND DEVICE In a data-processing method, first result data may be obtained using a plurality of configurable coarse-granular elements, the first result data may be written into a memory that includes spatially separate first and second memory areas and that is connected via a bus t... | 06/17/2010 |
| 20100106914 | CONSISTENCY MODELS IN A DISTRIBUTED STORE Systems and methods that designate read/write consistency models based on requirements of a distributed store to increase performance or scale. Such sever loads can be determined via a plurality of mechanisms, including delays in responses by the primary node; setting p... | 04/29/2010 |
| 20100088473 | VECTOR COMPUTER SYSTEM WITH CACHE MEMORY AND OPERATION METHOD THEREOF A vector computer system includes a vector processor configured to issue a vector store instruction which includes a plurality of store requests; a cache memory of a write back system provided between the vector processor and a main memory; and a write allocate determin... | 04/08/2010 |
| 20100030974 | SYSTEM AND METHOD FOR FETCHING INFORMATION TO A CACHE MODULE USING A WRITE BACK ALLOCATE ALGORITHM A write back allocate system that includes: (i) a store request circuit; (ii) a processor, adapted to generate a store request that comprises an information unit and an information unit address; and (iii) a cache module, connected to the store request circuit and to a h... | 02/04/2010 |
| 20100030971 | CACHE SYSTEM, CACHE SYSTEM CONTROL METHOD, AND INFORMATION PROCESSING APPARATUS To provide a cache system that can dynamically change a cache capacity by memory areas divided into plural. The cache system includes a line counter that counts the number of effective lines for each memory area. The effective line is a cache line in which effective cac... | 02/04/2010 |
| 20100005245 | SATISFYING MEMORY ORDERING REQUIREMENTS BETWEEN PARTIAL WRITES AND NON-SNOOP ACCESSES A method and apparatus for preserving memory ordering in a cache coherent link based interconnect in light of partial and non-coherent memory accesses is herein described. In one embodiment, when a conflict associated with a partial memory access, such as a partial writ... | 01/07/2010 |
| 20090300289 | Reducing back invalidation transactions from a snoop filter In one embodiment, the present invention includes a method for receiving an indication of a pending capacity eviction from a caching agent, determining whether an invalidating writeback transaction from the caching agent is likely for a cache line associated with the pe... | 12/03/2009 |
