Bizarre Patents
Wearable Device For Feeding and Observing Birds and Other Flying Animals
A device for feeding and observing flying animals comprising a hat, a support mounted on the hat and extending outward from the hat, and a feeder mounted on the support.
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| Application No. | Application Title | Issue Date |
| 20120131282 | Providing A Directory Cache For Peripheral Devices In one embodiment, the present invention includes a processor having at least one core and uncore logic. The uncore logic can include a home agent to act as a guard to control access to a memory region. Either in the home agent or another portion of the uncore logic, a ... | 05/24/2012 |
| 20120084498 | TRACKING WRITTEN ADDRESSES OF A SHARED MEMORY OF A MULTI-CORE PROCESSOR Described embodiments provide a method of controlling processing flow in a network processor having one or more processing modules. A given one of the processing modules loads a script into a compute engine. The script includes instructions for the compute engine. The g... | 04/05/2012 |
| 20120054439 | METHOD AND APPARATUS FOR ALLOCATING CACHE BANDWIDTH TO MULTIPLE PROCESSORS The present invention provides a method and apparatus for allocating cache bandwidth to multiple processors. One embodiment of the method includes delaying, at a local device associated with a local cache, a first cache probe from a non-local device to the local cache f... | 03/01/2012 |
| 20120054158 | Reduced Disk Space Standby A method and system for replicating database data is provided. One or more standby database replicas can be used for servicing read-only queries, and the amount of storage required is scalable in the size of the primary database storage. One technique is described for c... | 03/01/2012 |
| 20120042121 | Scatter-Gather Intelligent Memory Architecture For Unstructured Streaming Data On Multiprocessor Systems A scatter/gather technique optimizes unstructured streaming memory accesses, providing off-chip bandwidth efficiency by accessing only useful data at a fine granularity, and off-loading memory access overhead by supporting address calculation, data shuffling, and format... | 02/16/2012 |
| 20120042132 | STORAGE SYSTEM WITH MIDDLE-WAY LOGICAL VOLUME A storage system is disclosed including storage devices configured to store data, and a logical storage volume coupled to the storage devices and configured to store a subset of the data as segments. The storage system also includes a controller including a cache and me... | 02/16/2012 |
| 20120005432 | Reducing Cache Probe Traffic Resulting From False Data Sharing Disclosed herein are a processing unit and a multi-processing unit system that implement a cache-coherency method. Such a multi-processing unit system includes a main memory, a first processing unit, and a second processing unit. The first processing unit and the second... | 01/05/2012 |
| 20120005668 | STORAGE CONTROLLER COUPLED TO STORAGE APPARATUS A storage controller comprises a cache storage used as a cache of an external storage and a control processor coupled to the cache storage. The control processor comprises an internal access function and an external access function. The internal access function transmit... | 01/05/2012 |
| 20120005433 | RESPONSE HEADER INVALIDATION Systems, methods, and other embodiments associated with content invalidation are described. One example method includes providing an invalidation directive in a header of a response.... | 01/05/2012 |
| 20110320696 | EDRAM REFRESH IN A HIGH PERFORMANCE CACHE ARCHITECTURE A memory refresh requestor, a memory request interpreter, a cache memory, and a cache controller on a single chip. The cache controller configured to receive a memory access request, the memory access request for a memory address range in the cache memory, detect that t... | 12/29/2011 |
| 20110320738 | Maintaining Cache Coherence In A Multi-Node, Symmetric Multiprocessing Computer Maintaining cache coherence in a multi-node, symmetric multiprocessing computer, the computer composed of a plurality of compute nodes, including, broadcasting upon a cache miss by the first compute node to other compute nodes a request for the cache line; if at least t... | 12/29/2011 |
| 20110320739 | DISCOVERY OF NETWORK SERVICES Discovery of network services consumable by a client executing on a first device. A request is received from the client for a list of services. There is a determination of whether a second device on the network which maintains a current list of services can or can not b... | 12/29/2011 |
| 20110320727 | DYNAMIC CACHE QUEUE ALLOCATION BASED ON DESTINATION AVAILABILITY An apparatus for controlling operation of a cache includes a first command queue, a second command queue and an input controller configured to receive requests having a first command type and a second command type and to assign a first request having the first command t... | 12/29/2011 |
| 20110320737 | Main Memory Operations In A Symmetric Multiprocessing Computer Main memory operation in a symmetric multiprocessing computer, the computer comprising one or more processors operatively coupled through a cache controller to at least one cache of main memory, the main memory shared among the processors, the computer further comprisin... | 12/29/2011 |
| 20110320863 | DYNAMIC RE-ALLOCATION OF CACHE BUFFER SLOTS Dynamic re-allocation of cache buffer slots includes moving data out of a reserved buffer slot upon detecting an error in the reserved buffer slot, creating a new buffer slot, and storing the data moved out of the reserved buffer slot in the new buffer slot.... | 12/29/2011 |
| 20110314227 | Horizontal Cache Persistence In A Multi-Compute Node, Symmetric Multiprocessing Computer Horizontal cache persistence in a multi-compute node, SMP computer, including, responsive to a determination to evict a cache line on a first one of the compute nodes, broadcasting by a first compute node an eviction notice for the cache line; transmitting the state of ... | 12/22/2011 |
| 20110314228 | Maintaining Cache Coherence In A Multi-Node, Symmetric Multiprocessing Computer Maintaining cache coherence in a multi-node, symmetric multiprocessing computer, the computer composed of a plurality of compute nodes, including, broadcasting upon a cache miss by a first compute node a request for a cache line; transmitting from each of the other comp... | 12/22/2011 |
| 20110307894 | Redundant Multithreading Processor A redundant multithreading processor is presented. In one embodiment, the processor performs execution of a thread and its duplicate thread in parallel and determines, when in a redundant multithreading mode, whether or not to synchronize an operation of the thread and ... | 12/15/2011 |
| 20110307653 | CACHE COHERENCE PROTOCOL FOR PERSISTENT MEMORIES Subject matter disclosed herein relates to cache coherence of a processor system that includes persistent memory.... | 12/15/2011 |
| 20110302374 | LOCAL AND GLOBAL MEMORY REQUEST PREDICTOR A method, circuit arrangement, and design structure utilize broadcast prediction data to determine whether to globally broadcast a memory request in a computing system of the type that includes a plurality of nodes, each node including a plurality of processing units. T... | 12/08/2011 |
| 20110296116 | System and Method for Aggregating Core-Cache Clusters in Order to Produce Multi-Core Processors According to one embodiment of the invention, a processor comprises a memory, a plurality of core-cache clusters and a scalability agent unit that operates as an interface between an on-die interconnect and multiple core-cache clusters. The scalability agent operates in... | 12/01/2011 |
| 20110296115 | Assigning Memory to On-Chip Coherence Domains A mechanism is provided for assigning memory to on-chip cache coherence domains. The mechanism assigns caches within a processing unit to coherence domains. The mechanism then assigns chunks of memory to the coherence domains. The mechanism monitors applications running... | 12/01/2011 |
| 20110289257 | METHOD AND APPARATUS FOR ACCESSING CACHE MEMORY A request for reading data from a memory location of a main memory is received, the memory location being identified by a physical memory address. In response to the request, a cache memory is accessed based on the physical memory address to determine whether the cache ... | 11/24/2011 |
| 20110276762 | COORDINATED WRITEBACK OF DIRTY CACHELINES A data processing system includes a processor core and a cache memory hierarchy coupled to the processor core. The cache memory hierarchy includes at least one upper level cache and a lowest level cache. A memory controller is coupled to the lowest level cache and to a ... | 11/10/2011 |
| 20110276763 | MEMORY BUS WRITE PRIORITIZATION A data processing system includes a multi-level cache hierarchy including a lowest level cache, a processor core coupled to the multi-level cache hierarchy, and a memory controller coupled to the lowest level cache and to a memory bus of a system memory. The memory cont... | 11/10/2011 |
| 20110264865 | TECHNIQUES FOR DIRECTORY SERVER INTEGRATION Techniques for directory server integration are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for directory server integration comprising setting one or more parameters determining a range of permissible expiration times f... | 10/27/2011 |
| 20110258394 | MERGING DATA IN AN L2 CACHE MEMORY A method for merging data including receiving a request from an input/output device to merge a data, wherein a merge of the data includes a manipulation of the data, determining that the data exists in a local cache memory that is in local communication with the input/o... | 10/20/2011 |
| 20110252202 | SYSTEM AND METHOD FOR PROVIDING L2 CACHE CONFLICT AVOIDANCE A system provides a cache memory coherency mechanism within a multi-processor computing system utilizing a shared memory space across the multiple processors. The system possesses a store address list for storing cache line addresses corresponding to a cache line write ... | 10/13/2011 |
| 20110238925 | CACHE CONTROLLER AND METHOD OF OPERATION In one embodiment, there are described a sectored cache system and method of operation. A cache data block comprises separately updatable cache sectors. A common tag block contains metadata for the cache sectors of the data block and is writable as a whole. A pending al... | 09/29/2011 |
| 20110238926 | Method And Apparatus For Supporting Scalable Coherence On Many-Core Products Through Restricted Exposure In one embodiment, a multi-core processor having cores each associated with a cache memory, can operate such that when a first core is to access data owned by a second core present in a cache line associated with the second core, responsive to a request from the first c... | 09/29/2011 |
| 20110231614 | ACCELERATING MEMORY OPERATIONS USING VIRTUALIZATION INFORMATION A method of accelerating memory operations using virtualization information includes executing a hypervisor on hardware resources of a computing system. A plurality of domains are created under the control of the hypervisor, are created. Each domain is allocated memory ... | 09/22/2011 |
| 20110225372 | CONCURRENT, COHERENT CACHE ACCESS FOR MULTIPLE THREADS IN A MULTI-CORE, MULTI-THREAD NETWORK PROCESSOR Described embodiments provide a packet classifier of a network processor having a plurality of processing modules. A scheduler generates a thread of contexts for each tasks generated by the network processor corresponding to each received packet. The thread corresponds ... | 09/15/2011 |
| 20110208920 | FACILITATING SERVER RESPONSE OPTIMIZATION A configuration of cached information stored within a cache is determined. One or more character omission rules are determined by: identifying the one or more optimizable characters based on the configuration, where the one or more optimizable characters are characters ... | 08/25/2011 |
| 20110202729 | EXECUTING ATOMIC STORE DISJOINT INSTRUCTIONS A disjoint instruction for accessing operands in memory while executing in a processor of a plurality of processes interrogates a state indicator settable by other processors to determine if the disjoint instruction accessed the operands without an intervening store ope... | 08/18/2011 |
| 20110202730 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND COMPUTER-READABLE RECORDING MEDIUM An information processing apparatus according to the present invention is arranged in a client terminal connected to a server storing data via a network, wherein the information processing apparatus receives requests from one or a plurality of applications in the client... | 08/18/2011 |
| 20110202728 | METHODS AND APPARATUS FOR MANAGING CACHE PERSISTENCE IN A STORAGE SYSTEM USING MULTIPLE VIRTUAL MACHINES Methods and systems for assuring persistence of battery backed cache memory in a storage system comprising multiple virtual machines. In one exemplary embodiment, an additional process is added to the storage controller that senses the loss of power and copies the entir... | 08/18/2011 |
| 20110202731 | CACHE WITHIN A CACHE In a cache memory, energy and other efficiencies can be realized by saving a result of a cache directory lookup for sequential accesses to a same memory address. Where the cache is a point of coherence for speculative execution in a multiprocessor system, with directory... | 08/18/2011 |
| 20110202793 | FAILURE SYSTEM FOR DOMAIN NAME SYSTEM CLIENT A method performed by a domain name service client includes storing DNS entries in a local cache; sending a DNS query to another device to obtain an update to one of the DNS entries; determining whether a DNS response is received; and resetting a time-to-live (TTL) time... | 08/18/2011 |
| 20110202726 | Apparatus and method for handling data in a cache A data processing apparatus for forming a portion of a coherent cache system comprises at least one master device for performing data processing operations, and a cache coupled to the at least one master device and arranged to store data values for access by that at lea... | 08/18/2011 |
| 20110197033 | Cache Used Both as Cache and Staging Buffer In one embodiment, a cache comprises a data memory comprising a plurality of data entries, each data entry having capacity to store a cache block of data, and a cache control unit coupled to the data memory. The cache control unit is configured to dynamically allocate a... | 08/11/2011 |
