Bizarre Patents
Pet Toilet-Like Water Disk and Food Storage
One pet-friendly inventor patented "a device for watering pets, e.g., a dog or cat." The device, he helpfully noted, "has the general shape of a toilet."
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| Application No. | Application Title | Issue Date |
| 20100268891 | Allocation of memory space to individual processor cores Techniques are generally described for a multi-core processor with a plurality of processor cores. At least one cache is accessible to at least two of the plurality of processor cores. The multi-core processor can be configured for separately allocating a memory space w... | 10/21/2010 |
| 20100153655 | STORE QUEUE WITH STORE-MERGING AND FORWARD-PROGRESS GUARANTEES Some embodiments of the present invention provide a system that performs stores in a memory system. During operation, the system performs a store for a first thread, which involves creating an entry for the store in a store queue for the first thread. It also involves a... | 06/17/2010 |
| 20100122013 | DATA STRUCTURE FOR ENFORCING CONSISTENT PER-PHYSICAL PAGE CACHEABILITY ATTRIBUTES A data structure for enforcing consistent per-physical page cacheability attributes is disclosed. The data structure is used with a method for enforcing consistent per-physical page cacheability attributes, which maintains memory coherency within a processor addressing ... | 05/13/2010 |
| 20090204769 | Method to Bypass Cache Levels in a Cache Coherent System Embodiments of the invention provide methods and apparatus for selectively bypassing cache levels when processing non-reusable transient data in a cache coherent system. To selectively bypass cache levels a page table entry (PTE) mechanism may be employed. To limit the ... | 08/13/2009 |
| 20090157975 | Memory-centric Page Table Walker The page table walker is moved from its conventional location in the memory management unit associated with the data processor to a location in main memory i.e. the main memory controller. As a result, an implementation is provided wherein the processing of requests for... | 06/18/2009 |
| 20050182905 | Data accesses in data processing A data processor comprising: a control register operable to store a cache control value; and data accessing logic responsive to a data access instruction and to said cache control value to look for data to be accessed in a cache if said cache control value has a predete... | 08/18/2005 |
| 20050044325 | Programmably disabling one or more cache entries A cache may be programmed to disable one or more entries from allocation for storing memory data (e.g. in response to a memory transaction which misses the cache). Furthermore, the cache may be programmed to select which entries of the cache are disabled from allocation... | 02/24/2005 |
