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| Application No. | Application Title | Issue Date |
| 20120131269 | ADAPTIVE MEMORY SYSTEM FOR ENHANCING THE PERFORMANCE OF AN EXTERNAL COMPUTING DEVICE An adaptive memory system is provided for improving the performance of an external computing device. The adaptive memory system includes a single controller, a first memory type (e.g., Static Random Access Memory or SRAM), a second memory type (e.g., Dynamic Random Acce... | 05/24/2012 |
| 20120110269 | PREFETCH INSTRUCTION Techniques are disclosed relating to prefetching data from memory. In one embodiment, an integrated circuit may include a processor containing an execution core and a data cache. The execution core may be configured to receive an instance of a prefetch instruction that ... | 05/03/2012 |
| 20120084511 | INEFFECTIVE PREFETCH DETERMINATION AND LATENCY OPTIMIZATION A processor of an information handling system (IHS) initiates an L3 cache prefetch operation in response to a demand load during instruction processing. The processor selects an L3 cache prefetch at random for tracking as a target prefetched instruction. The processor i... | 04/05/2012 |
| 20120072674 | DOUBLE-BUFFERED DATA STORAGE TO REDUCE PREFETCH GENERATION STALLS A prefetch unit includes a program prefetch address generator that receives memory read requests and in response to addresses associated with the memory read request generates prefetch addresses and stores the prefetch addresses in slots of the prefetch unit buffer. Eac... | 03/22/2012 |
| 20120072671 | PREFETCH STREAM FILTER WITH FIFO ALLOCATION AND STREAM DIRECTION PREDICTION A prefetch filter receives a memory read request having an associated address for accessing data that is stored in a line of memory. An address window is determined that has an address range that encompasses an address space that is twice as large as the line of memory.... | 03/22/2012 |
| 20120072673 | SPECULATION-AWARE MEMORY CONTROLLER ARBITER A memory arbiter minimizes latency of memory accesses in a system having multiple processors. The memory arbiter improves overall system performance by managing the memory requests from each processor individually before those requests are sent to a central memory arbit... | 03/22/2012 |
| 20120072672 | PREFETCH ADDRESS HIT PREDICTION TO REDUCE MEMORY ACCESS LATENCY A prefetch unit receives a memory read request having an associated address for accessing data that is stored in memory. A next predicted address is determined in response to a prefetch address stored in a slot of an array for storing portions of predicted addresses and... | 03/22/2012 |
| 20120054448 | METHOD AND APPARATUS FOR ADAPTING AGGRESSIVENESS OF A PRE-FETCHER The present invention provides a method and apparatus for adapting aggressiveness of a pre-fetcher in a processor-based system. One embodiment includes modifying a rate for pre-fetching data from a memory into one or more caches by comparing a first address of a memory ... | 03/01/2012 |
| 20120054449 | METHOD AND APPARATUS FOR FUZZY STRIDE PREFETCH In one embodiment, the present invention includes a prefetching engine to detect when data access strides in a memory fall into a range, to compute a predicted next stride, to selectively prefetch a cache line using the predicted next stride, and to dynamically control ... | 03/01/2012 |
| 20120054443 | PARTIALLY SECTORED CACHE The present invention provides embodiments of a partially sectored cache. One embodiment of the apparatus includes a cache that includes a tag array for storing information indicating a plurality of tags and a data array for storing a plurality of lines. A first portion... | 03/01/2012 |
| 20120036327 | DYNAMIC LOOK-AHEAD EXTENT MIGRATION FOR TIERED STORAGE ARCHITECTURES A method for migrating extents between extent pools in a tiered storage architecture maintains a data access profile for an extent over a period of time. Using the data access profile, the method generates an extent profile graph that predicts data access rates for the ... | 02/09/2012 |
| 20120030431 | PREDICTIVE SEQUENTIAL PREFETCHING FOR DATA CACHING A system for prefetching memory in caching systems includes a processor that generates requests for data. A cache of a first level stores memory lines retrieved from a lower level memory in response to references to addresses generated by the processor's requests for da... | 02/02/2012 |
| 20120030275 | PROVIDING STATUS INFORMATION FOR COMPONENTS IN A DISTRIBUTED LANDSCAPE In a distributed landscape, different levels of data caches, such as a memory cache and prefetch tables, are provided for storing status and other information about a remote system to a client. Status information may be provided to the client from a memory cache if avai... | 02/02/2012 |
| 20120011325 | METHODS AND SYSTEMS FOR CACHING DATA USING BEHAVIORAL EVENT CORRELATIONS A method is disclosed including a client accessing a cache for a value of an object based on an object identification (ID), initiating a request to a cache loader if the cache does not include a value for the object, the cache loader performing a lookup in an object tab... | 01/12/2012 |
| 20110283067 | Target Memory Hierarchy Specification in a Multi-Core Computer Processing System Target memory hierarchy specification in a multi-core computer processing system is provided including a system for implementing prefetch instructions. The system includes a first core processor, a dedicated cache corresponding to the first core processor, and a second ... | 11/17/2011 |
| 20110276786 | Shared Prefetching to Reduce Execution Skew in Multi-Threaded Systems Mechanisms are provided for optimizing code to perform prefetching of data into a shared memory of a computing device that is shared by a plurality of threads that execute on the computing device. A memory stream of a portion of code that is shared by the plurality of t... | 11/10/2011 |
| 20110271058 | Method, system and apparatus for identifying a cache line A method of identifying a cache line of a cache memory (180) for replacement, is disclosed. Each cache line in the cache memory has a stored sequence number and a stored transaction data stream identifying label. A request (e.g., 400) associated with a lab... | 11/03/2011 |
| 20110264864 | Prefetch Unit In one embodiment, a processor comprises a prefetch unit coupled to a data cache. The prefetch unit is configured to concurrently maintain a plurality of separate, active prefetch streams. Each prefetch stream is either software initiated via execution by the processor ... | 10/27/2011 |
| 20110264860 | MULTI-MODAL DATA PREFETCHER A microprocessor includes first and second cache memories occupying distinct hierarchy levels, the second backing the first. A prefetcher monitors load operations and maintains a recent history of the load operations from a cache line and determines whether the recent h... | 10/27/2011 |
| 20110246722 | ADAPTIVE BLOCK PRE-FETCHING METHOD AND SYSTEM A method and system may include fetching a first pre-fetched data block having a first length greater than the length of a first requested data block, storing the first pre-fetched data block in a cache, and then fetching a second pre-fetched data block having a second ... | 10/06/2011 |
| 20110238923 | COMBINED L2 CACHE AND L1D CACHE PREFETCHER A microprocessor includes a first-level cache memory, a second-level cache memory, and a data prefetcher that detects a predominant direction and pattern of recent memory accesses presented to the second-level cache memory and prefetches cache lines into the second-leve... | 09/29/2011 |
| 20110238921 | ANTICIPATORY RESPONSE PRE-CACHING Interaction between a client and a service in which the service responds to requests from the client. In addition to responding to specific client requests, the service also anticipates or speculates about what the client may request in the future. Rather than await the... | 09/29/2011 |
| 20110238922 | BOUNDING BOX PREFETCHER A data prefetcher in a microprocessor having a cache memory receives memory accesses each to an address within a memory block. The access addresses are non-monotonically increasing or decreasing as a function of time. As the accesses are received, the prefetcher maintai... | 09/29/2011 |
| 20110225371 | DATA PREFETCH FOR SCSI REFERRALS A method for communication between an initiator system and a storage cluster. The method comprises receiving an initial I/O request from the initiator system to a first storage system; providing a referral response from the first storage system to the initiator system, ... | 09/15/2011 |
| 20110219196 | MEMORY HUB WITH INTERNAL CACHE AND/OR MEMORY ACCESS PREDICTION A computer system includes a memory hub for coupling a processor to a plurality of synchronous dynamic random access memory (“SDRAM”) devices. The memory hub includes a processor interface coupled to the processor and a plurality of memory interfaces coupled to resp... | 09/08/2011 |
| 20110219195 | PRE-FETCHING OF DATA PACKETS Some of the embodiments of the present disclosure provide a method comprising receiving a data packet, and storing the received data packet in a memory; generating a descriptor for the data packet, the descriptor including information for fetching at least a portion of ... | 09/08/2011 |
| 20110219190 | CACHE WITH RELOAD CAPABILITY AFTER POWER RESTORATION A method and apparatus for repopulating a cache are disclosed. At least a portion of the contents of the cache are stored in a location separate from the cache. Power is removed from the cache and is restored some time later. After power has been restored to the cache, ... | 09/08/2011 |
| 20110219194 | DATA RELAYING APPARATUS AND METHOD FOR RELAYING DATA BETWEEN DATA A data relaying apparatus and method capable of relaying data in a highly efficient manner. Data of a predetermined read-ahead size is acquired from the storage apparatus from a top address indicated by a data read request to temporarily store the data as temporary stor... | 09/08/2011 |
| 20110213924 | METHODS FOR ADAPTING PERFORMANCE SENSITIVE OPERATIONS TO VARIOUS LEVELS OF MACHINE LOADS For each of a plurality of memory access routines having different access timing characteristic, a redundant array of independent disk (RAID) stack executes the memory access routine to load predetermined data from a main memory to a register of a processor of a data pr... | 09/01/2011 |
| 20110208918 | MOVE ELIMINATION AND NEXT PAGE PREFETCHER Methods and apparatus relating to a hardware move elimination and/or next page prefetching are described. In some embodiments, a logic may provide hardware move eliminations based on stored data. In an embodiment, a next page prefetcher is disclosed. Other embodiments a... | 08/25/2011 |
| 20110208919 | CACHING BASED ON SPATIAL DISTRIBUTION OF ACCESSES TO DATA STORAGE DEVICES Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for quantifying a spatial distribution of accesses to storage systems and for determining spatial locality of references to storage addresses in the storage systems, are d... | 08/25/2011 |
| 20110197031 | Update Handler For Multi-Channel Cache Disclosed herein is a miss handler for a multi-channel cache memory, and a method that includes determining a need to update a multi-channel cache memory due at least to one of an occurrence of a cache miss or a data prefetch being needed. The method further includes op... | 08/11/2011 |
| 20110173398 | TWO DIFFERENT PREFETCHING COMPLEMENTARY ENGINES OPERATING SIMULTANEOUSLY A prefetch system improves a performance of a parallel computing system. The parallel computing system includes a plurality of computing nodes. A computing node includes at least one processor and at least one memory device. The prefetch system includes at least one str... | 07/14/2011 |
| 20110173396 | Performing High Granularity Prefetch from Remote Memory into a Cache on a Device without Change in Address Provided is a method, which may be performed on a computer, for prefetching data over an interface. The method may include receiving a first data prefetch request for first data of a first data size stored at a first physical address corresponding to a first virtual add... | 07/14/2011 |
| 20110173397 | PROGRAMMABLE STREAM PREFETCH WITH RESOURCE OPTIMIZATION A stream prefetch engine performs data retrieval in a parallel computing system. The engine receives a load request from at least one processor. The engine evaluates whether a first memory address requested in the load request is present and valid in a table. The engine... | 07/14/2011 |
| 20110161587 | PROACTIVE PREFETCH THROTTLING According to a method of data processing, a memory controller receives a plurality of data prefetch requests from multiple processor cores in the data processing system, where the plurality of prefetch load requests include a data prefetch request issued by a particular... | 06/30/2011 |
| 20110161592 | Dynamic system reconfiguration In some embodiments system reconfiguration code and data to be used to perform a dynamic hardware reconfiguration of a system including a plurality of processor cores is cached and any direct or indirect memory accesses during the dynamic hardware reconfiguration are pr... | 06/30/2011 |
| 20110145502 | META-DATA BASED DATA PREFETCHING A technique for prefetching data into a cache memory system includes prefetching data based on meta information indicative of data access patterns. A method includes tagging data of a program with meta information indicative of data access patterns. The method includes ... | 06/16/2011 |
| 20110145508 | AUTOMATIC DETERMINATION OF READ-AHEAD AMOUNT Read-ahead of data blocks in a storage system is performed based on a policy. The policy is stochastically selected from a plurality of policies in respect to probabilities. The probabilities are calculated based on past performances, also referred to as rewards. Polici... | 06/16/2011 |
| 20110145507 | METHOD OF REDUCING RESPONSE TIME FOR DELIVERY OF VEHICLE TELEMATICS SERVICES A method of operating a predictive data cache includes receiving a request for telematics service from a telematics service requester, determining the subject matter of the request, querying a predictive data cache to determine if the predictive data cache includes a se... | 06/16/2011 |
