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| Application No. | Application Title | Issue Date |
| 20120084515 | CACHE MEMORY CONTROLLER AND METHOD FOR REPLACING A CACHE BLOCK The present disclosure relates to a cache memory controller for controlling a set-associative cache memory, in which two or more blocks are arranged in the same set, the cache memory controller including a content modification status monitoring unit for monitoring wheth... | 04/05/2012 |
| 20120084514 | LOCKING A CACHE LINE FOR WRITE OPERATIONS ON A BUS Provided are a computer program product, system, and method for locking a cache line for a burst write operations on a bus. A cache line is allocated in a cache for a target address. A lock is set for the cache line, wherein setting the lock prevents the data in the cac... | 04/05/2012 |
| 20120072671 | PREFETCH STREAM FILTER WITH FIFO ALLOCATION AND STREAM DIRECTION PREDICTION A prefetch filter receives a memory read request having an associated address for accessing data that is stored in a line of memory. An address window is determined that has an address range that encompasses an address space that is twice as large as the line of memory.... | 03/22/2012 |
| 20120072670 | METHOD FOR COUPLING SUB-LUN LOAD MEASURING METADATA SIZE TO STORAGE TIER UTILIZATION IN DYNAMIC STORAGE TIERING A method for metadata management in a storage system configured for supporting sub-LUN tiering. The method may comprise providing a metadata queue of a specific size; determining whether the metadata for a particular sub-LUN is cached in the metadata queue; updating the... | 03/22/2012 |
| 20120054447 | METHOD AND SYSTEM FOR REMOVING CACHE BLOCKS A method for removing cache blocks from a cache queue includes detecting a first cache miss for the cache queue, identifying, within the cache queue, a new cache block storing a value of a storage block, calculating an estimated cache miss cost for a storage container h... | 03/01/2012 |
| 20120054446 | IMPLEMENTING CACHE OFFLOADING A computer-implemented method, computer program product, and system are provided for implementing a cache offloader. A current cache memory usage is compared with a memory threshold. Responsive to the current cache memory usage exceeding the memory threshold, cache reco... | 03/01/2012 |
| 20120017050 | LOCAL CACHE PROVIDING FAST CHANNEL CHANGE Methods, systems, and apparatuses facilitate the processing of requests for media content, which can originate from a request by a user or device to change a channel. The media content for a subset of channels can be locally cached and fetched for quick retrieval.... | 01/19/2012 |
| 20120011324 | SYSTEM AND METHOD FOR MANAGING LARGE FILESYSTEM-BASED CACHES Embodiments disclosed herein utilize statistical approximations to manage large filesystem-based caches based on imperfect information. When removing entries from a large cache, which may have a million or more entries, the cache manager does not need to find the absolu... | 01/12/2012 |
| 20110307447 | Inline Wire Speed Deduplication System Systems for performing inline wire speed data deduplication are described herein. Some embodiments include a device for inline data deduplication that includes one or more input ports for receiving an input data stream containing duplicates, one or more output ports for... | 12/15/2011 |
| 20110289277 | INFORMATION PROCESSING SYSTEM, INFORMATION PROCESSING METHODS AND PROGRAMS The present invention obtains with high precision, in a storage system, the effect of additional installation or removal of cache memory, that is, the change of the cache hit rate and the performance of the storage system at that time. For achieving this, when executing... | 11/24/2011 |
| 20110238920 | BOUNDING BOX PREFETCHER WITH REDUCED WARM-UP PENALTY ON MEMORY BLOCK CROSSINGS A microprocessor includes a cache memory and a data prefetcher. The data prefetcher detects a pattern of memory accesses within a first memory block and prefetch into the cache memory cache lines from the first memory block based on the pattern. The data prefetcher also... | 09/29/2011 |
| 20110231598 | MEMORY SYSTEM AND CONTROLLER According to one embodiment, a memory system includes a first memory that is nonvolatile, a second memory, and a controller that performs data transfer between a host device and the first memory by using the second memory. The controller caches data of each write comman... | 09/22/2011 |
| 20110219193 | PROCESSOR AND MEMORY CONTROL METHOD A processor and a memory management method are provided. The processor includes a processor core, a cache which transceives data to/from the processor core via a single port, and stores the data accessed by the processor core, and a Scratch Pad Memory (SPM) which transc... | 09/08/2011 |
| 20110161598 | DUAL TIMEOUT CACHING Embodiments of the present invention provide a method, system and computer program product for dual timer fragment caching. In an embodiment of the invention, a dual timer fragment caching method can include establishing both a soft timeout and also a hard timeout for e... | 06/30/2011 |
| 20110161548 | Efficient Multi-Level Software Cache Using SIMD Vector Permute Functionality A cache manager receives a request for data, which includes a requested effective address. The cache manager determines whether the requested effective address matches a most recently used effective address stored in a mapped tag vector. When the most recently used effe... | 06/30/2011 |
| 20110153953 | SYSTEMS AND METHODS FOR MANAGING LARGE CACHE SERVICES IN A MULTI-CORE SYSTEM A multi-core system that includes a 64-bit cache storage and a 32-bit memory storage that stores a 32-bit cache object directory. One or more cache engines execute on cores of the multi-core system to retrieve objects from the 64-bit cache, create cache directory object... | 06/23/2011 |
| 20110125972 | INFORMATION RECORDING DEVICE AND INFORMATION RECORDING METHOD In one embodiment, there is provided an information recording device that includes: a plurality of cache buffers on which writing is performed in response to an external write request; and a controller configured to determine, according to an LRU algorithm, which of the... | 05/26/2011 |
| 20110099333 | MECHANISM FOR EFFECTIVELY CACHING STREAMING AND NON-STREAMING DATA PATTERNS A method and apparatus for efficiently caching streaming and non-streaming data is described herein. Software, such as a compiler, identifies last use streaming instructions/operations that are the last instruction/operation to access streaming data for a number of inst... | 04/28/2011 |
| 20110093654 | Memory control A data processing apparatus 1 comprises data processing circuitry 2, a memory 8 for storing data and a cache memory 5 for storing cached data from the memory 8. The cache memory 5 is partitioned into cache segments 12 whi... | 04/21/2011 |
| 20110087845 | BURST-BASED CACHE DEAD BLOCK PREDICTION The present disclosure generally relates to cache memory systems and/or techniques to identify dead cache blocks in cache memory systems. Example systems may include a cache memory that is accessible by a cache client. The cache memory may include a plurality of storage... | 04/14/2011 |
| 20110072218 | PREFETCH PROMOTION MECHANISM TO REDUCE CACHE POLLUTION A processor is disclosed. The processor includes an execution core, a cache memory, and a prefetcher coupled to the cache memory. The prefetcher is configured to fetch a first cache line from a lower level memory and to load the cache line into the cache. The cache is f... | 03/24/2011 |
| 20110055485 | EFFICIENT PSEUDO-LRU FOR COLLIDING ACCESSES An apparatus for allocating entries in a set associative cache memory includes an array that provides a first pseudo-least-recently-used (PLRU) vector in response to a first allocation request from a first functional unit. The first PLRU vector specifies a first entry f... | 03/03/2011 |
| 20110055482 | SHARED CACHE RESERVATION Various example embodiments are disclosed. According to an example embodiment, a shared cache may be configured to determine whether a word requested by one of the L1 caches is currently stored in the L2 shared cache, read the requested word from the main memory based o... | 03/03/2011 |
| 20110022805 | Wait-Free Parallel Data Cache A system and method for managing a data cache in a central processing unit (CPU) of a database system. A method executed by a system includes the processing steps of adding an ID of a page p into a page holder queue of the data cache, executing a memory barrier store-lo... | 01/27/2011 |
| 20110010502 | Cache Implementing Multiple Replacement Policies In an embodiment, a cache stores tags for cache blocks stored in the cache. Each tag may include an indication identifying which of two or more replacement policies supported by the cache is in use for the corresponding cache block, and a replacement record indicating t... | 01/13/2011 |
| 20100325365 | SECTORED CACHE REPLACEMENT ALGORITHM FOR REDUCING MEMORY WRITEBACKS An improved sectored cache replacement algorithm is implemented via a method and computer program product. The method and computer program product select a cache sector among a plurality of cache sectors for replacement in a computer system. The method may comprise sele... | 12/23/2010 |
| 20100318744 | DIFFERENTIAL CACHING MECHANISM BASED ON MEDIA I/O SPEED A method for allocating space in a cache based on media I/O speed is disclosed herein. In certain embodiments, such a method may include storing, in a read cache, cache entries associated with faster-responding storage devices and cache entries associated with slower-re... | 12/16/2010 |
| 20100318745 | Dynamic Content Caching and Retrieval This disclosure provides techniques for dynamic content caching and retrieval. For example, a computing device includes cache memory dedicated to temporarily caching data of one or more applications of the computing device. The computing device also includes storage mem... | 12/16/2010 |
| 20100312970 | Cache Management Through Delayed Writeback The illustrative embodiments provide a method, apparatus, and computer program product for managing a number of cache lines in a cache. In one illustrative embodiment, it is determined whether activity on a memory bus in communication with the cache exceeds a threshold ... | 12/09/2010 |
| 20100293337 | SYSTEMS AND METHODS OF TIERED CACHING The disclosure is related to data storage systems having multiple cache and to management of cache activity in data storage systems having multiple cache. In a particular embodiment, a data storage device includes a volatile memory having a first read cache and a first ... | 11/18/2010 |
| 20100293338 | CACHE CLEANUP AND LATCHING A low priority queue can be configured to list low priority removal candidates to be removed from a cache, with the low priority removal candidates being sorted in an order of priority for removal. A high priority queue can be configured to list high priority removal ca... | 11/18/2010 |
| 20100287339 | DEMAND BASED PARTITIONING OR MICROPROCESSOR CACHES Associativity of a multi-core processor cache memory to a logical partition is managed and controlled by receiving a plurality of unique logical processing partition identifiers into registration of a multi-core processor, each identifier being associated with a logical... | 11/11/2010 |
| 20100274974 | SYSTEM AND METHOD FOR REPLACING DATA IN A CACHE A system and method for replacing data in a cache utilizes cache block validity information, which contains information that indicates that data in a cache block is no longer needed for processing, to maintain least recently used information of cache blocks in a cache s... | 10/28/2010 |
| 20100275044 | CACHE ARCHITECTURE WITH DISTRIBUTED STATE BITS Embodiments that that distribute replacement policy bits and operate the bits in cache memories, such as non-uniform cache access (NUCA) caches, are contemplated. An embodiment may comprise a computing device, such as a computer having multiple processors or multiple co... | 10/28/2010 |
| 20100268882 | LOAD REQUEST SCHEDULING IN A CACHE HIERARCHY A system and method for tracking core load requests and providing arbitration and ordering of requests. When a core interface unit (CIU) receives a load operation from the processor core, a new entry in allocated in a queue of the CIU. In response to allocating the new ... | 10/21/2010 |
| 20100257320 | Cache Replacement Policy Techniques for replacing one or more blocks in a cache, the one or more blocks being associated with a plurality of data streams, are provided. The one or more blocks in the cache are grouped into one or more groups. Each group corresponding to one of the plurality of d... | 10/07/2010 |
| 20100235585 | DATA CACHING IN CONSOLIDATED NETWORK REPOSITORY System(s) and method(s) are provided for caching data in a consolidated network repository of information available to mobile and non-mobile networks, and network management systems. Data can be cached in response to request(s) for a data element or request(s) for an up... | 09/16/2010 |
| 20100217937 | Data processing apparatus and method A data processing apparatus is described which comprises a processor operable to execute a sequence of instructions and a cache memory having a plurality of cache lines operable to store data values for access by the processor when executing the sequence of instructions... | 08/26/2010 |
| 20100211731 | Hard Disk Drive with Attached Solid State Drive Cache Methods, systems, and computer programs for managing storage in a computer system using a solid state drive (SSD) read cache memory are presented. The method includes receiving a read request, which causes a miss in a cache memory. After the cache miss, the method deter... | 08/19/2010 |
| 20100191916 | Optimizing A Cache Back Invalidation Policy A method and a system for utilizing less recently used (LRU) bits and presence bits in selecting cache-lines for eviction from a lower level cache in a processor-memory sub-system. A cache back invalidation (CBI) logic utilizes LRU bits to evict only cache-lines within ... | 07/29/2010 |
