Did You Know...
...that a workman who left the soap mixing machine on too long was responsible for making Ivory Soap? He was so embarrassed by his mistake that he threw the mess in a stream. Imagine his dismay when the evidence of his error floated to the surface! Result: Ivory soap, the soap that floats.
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| Application No. | Application Title | Issue Date |
| 20120131280 | SYSTEMS AND METHODS FOR BACKING UP STORAGE VOLUMES IN A STORAGE SYSTEM Systems and methods for backing up storage volumes are provided. One system includes a primary side, a secondary side, and a network coupling the primary and secondary sides. The secondary side includes first and second VTS including a cache and storage tape. The first ... | 05/24/2012 |
| 20120131279 | MEMORY ELEMENTS FOR PERFORMING AN ALLOCATION OPERATION AND RELATED METHODS Apparatus for memory elements and related methods for performing an allocate operation are provided. An exemplary memory element includes a plurality of way memory elements and a replacement module coupled to the plurality of way memory elements. Each way memory element... | 05/24/2012 |
| 20120110111 | CACHE DEFEAT DETECTION AND CACHING OF CONTENT ADDRESSED BY IDENTIFIERS INTENDED TO DEFEAT CACHE Systems and methods for cache defeat detection are disclosed. Moreover, systems and methods for caching of content addressed by identifiers intended to defeat cache are further disclosed. In one aspect, embodiments of the present disclosure include a method, which may b... | 05/03/2012 |
| 20120084513 | CIRCUIT AND METHOD FOR DETERMINING MEMORY ACCESS, CACHE CONTROLLER, AND ELECTRONIC DEVICE A memory access determination circuit includes a counter that switches between a first reference value and a second reference value in accordance with a control signal to generate a count value based on the first reference value or the second reference value. A controll... | 04/05/2012 |
| 20120054447 | METHOD AND SYSTEM FOR REMOVING CACHE BLOCKS A method for removing cache blocks from a cache queue includes detecting a first cache miss for the cache queue, identifying, within the cache queue, a new cache block storing a value of a storage block, calculating an estimated cache miss cost for a storage container h... | 03/01/2012 |
| 20120054444 | EVICTING DATA FROM A CACHE VIA A BATCH FILE In an embodiment, a plurality of keys are evicted from a first cache at a primary server. A first key is evicted from the first cache because the first key satisfied a first evict policy during a first time range. A second key is evicted from the first cache because the... | 03/01/2012 |
| 20120054445 | METHOD AND SYSTEM FOR INSERTING CACHE BLOCKS A method of inserting cache blocks into a cache queue includes detecting a first cache miss for the cache queue, identifying a storage block receiving an access in response to the cache miss, calculating a first estimated cache miss cost for a first storage container th... | 03/01/2012 |
| 20120047330 | I/O EFFICIENCY OF PERSISTENT CACHES IN A STORAGE SYSTEM A system and method are disclosed for improving the efficiency of a storage system. At least one application-oriented property is associated with data to be stored on a storage system. Based on the at least one application-oriented property, a manner of implementing at ... | 02/23/2012 |
| 20120036326 | EFFICIENTLY SYNCHRONIZING WITH SEPARATED DISK CACHES In a method of synchronizing with a separated disk cache, the separated cache is configured to transfer cache data to a staging area of a storage device. An atomic commit operation is utilized to instruct the storage device to atomically commit the cache data to a mappi... | 02/09/2012 |
| 20120011323 | MEMORY SYSTEM AND MEMORY MANAGEMENT METHOD INCLUDING THE SAME A multi-processor system includes a first processor, a second processor communicable with the first processor, a first non-volatile memory for storing first codes and second codes to respectively boot the first and second processors, the first memory communicable with t... | 01/12/2012 |
| 20110320731 | ON DEMAND ALLOCATION OF CACHE BUFFER SLOTS Dynamic allocation of cache buffer slots includes receiving a request to perform an operation that requires a storage buffer slot, the storage buffer slot residing in a level of storage. The dynamic allocation of cache buffer slots also includes determining availability... | 12/29/2011 |
| 20110320730 | NON-BLOCKING DATA MOVE DESIGN A mechanism for data buffering is provided. A portion of a cache is allocated as buffer regions, and another portion of the cache is designated as random access memory (RAM). One of the buffer regions is assigned to a processor. A data block is stored to the one of the ... | 12/29/2011 |
| 20110320720 | Cache Line Replacement In A Symmetric Multiprocessing Computer Cache line replacement in a symmetric multiprocessing computer, the computer having a plurality of processors, a main memory that is shared among the processors, a plurality of cache levels including at least one high level of private caches and a low level shared cache... | 12/29/2011 |
| 20110307664 | Cache device for coupling to a memory device and a method of operation of such a cache device A cache device is provided for use in a data processing apparatus to store data values for access by an associated master device. Each data value has an associated memory location in a memory device, and the memory device is arranged as a plurality of blocks of memory l... | 12/15/2011 |
| 20110307666 | DATA CACHING METHOD Data caching for use in a computer system including a lower cache memory and a higher cache memory. The higher cache memory receives a fetch request. It is then determined by the higher cache memory the state of the entry to be replaced next. If the state of the entry t... | 12/15/2011 |
| 20110296112 | Reducing Energy Consumption of Set Associative Caches by Reducing Checked Ways of the Set Association Mechanisms for accessing a set associative cache of a data processing system are provided. A set of cache lines, in the set associative cache, associated with an address of a request are identified. Based on a determined mode of operation for the set, the following may ... | 12/01/2011 |
| 20110238919 | CONTROL OF PROCESSOR CACHE MEMORY OCCUPANCY Techniques are described for controlling processor cache memory within a processor system. Cache occupancy values for each of a plurality of entities executing the processor system can be calculated. A cache replacement algorithm uses the cache occupancy values when mak... | 09/29/2011 |
| 20110231613 | REMOTE STORAGE CACHING Disclosed is a storage system. A network interface device (NIC) receives network storage commands from a host. The NIC may cache the data to/from the storage commands in a solid-state disk. The NIC may respond to future network storage command by supplying the data from... | 09/22/2011 |
| 20110197033 | Cache Used Both as Cache and Staging Buffer In one embodiment, a cache comprises a data memory comprising a plurality of data entries, each data entry having capacity to store a cache block of data, and a cache control unit coupled to the data memory. The cache control unit is configured to dynamically allocate a... | 08/11/2011 |
| 20110197032 | CACHE COORDINATION BETWEEN DATA SOURCES AND DATA RECIPIENTS A data recipient configured to access a data source may exhibit improved performance by caching data items received from the data source. However, the cache may become stale unless the data recipient is informed of data source updates. Many subscription mechanisms are s... | 08/11/2011 |
| 20110191544 | Data Storage and Access A data cache wherein contents of the cache are arranged and organised according to a hierarchy. When a member of a first hierarchy is accessed, all contents of that member are copied to the cache. The cache may be arranged according to folders which contain data or bloc... | 08/04/2011 |
| 20110179227 | CACHE MEMORY AND METHOD FOR CACHE ENTRY REPLACEMENT BASED ON MODIFIED ACCESS ORDER A cache memory and method for controlling the cache memory. The cache memory selects, from an access address, a unique set from among a plurality of sets, each access set including a plurality of cache entries. Each cache entry holds unit data for caching. The cache mem... | 07/21/2011 |
| 20110173395 | TEMPERATURE-AWARE BUFFERED CACHING FOR SOLID STATE STORAGE A system and method for managing a cache includes monitoring a temperature of regions on a secondary storage based on a cumulative cost to access pages from each region of the secondary storage. Similar temperature pages are grouped in logical blocks. Data is written to... | 07/14/2011 |
| 20110161597 | Combined Memory Including a Logical Partition in a Storage Memory Accessed Through an IO Controller A computer system having a combined memory. A first logical partition of the combined memory is a main memory region in a storage memory. A second logical partition of the combined memory is a direct memory region in a main memory. A memory controller comprising a stora... | 06/30/2011 |
| 20110161589 | SELECTIVE CACHE-TO-CACHE LATERAL CASTOUTS A data processing system includes first and second processing units and a system memory. The first processing unit has first upper and first lower level caches, and the second processing unit has second upper and lower level caches. In response to a data request, a vict... | 06/30/2011 |
| 20110153950 | Cache memory, cache memory system, and method program for using the cache memory A cache memory includes: a plurality of MSHRs (Miss Status/Information Holding Registers); a memory access identification unit that identifies a memory access included in an accepted memory access request; and a memory access association unit that associates a given mem... | 06/23/2011 |
| 20110153949 | DELAYED REPLACEMENT OF CACHE ENTRIES A cache entry replacement unit can delay replacement of more valuable entries by replacing less valuable entries. When a miss occurs, the cache entry replacement unit can determine a cache entry for replacement (“a replacement entry”) based on a generic replacement ... | 06/23/2011 |
| 20110145506 | Replacing Cache Lines In A Cache Memory In one embodiment, the present invention includes a cache memory including cache lines that each have a tag field including a state portion to store a cache coherency state of data stored in the line and a weight portion to store a weight corresponding to a relative imp... | 06/16/2011 |
| 20110145505 | Assigning Cache Priorities to Virtual/Logical Processors and Partitioning a Cache According to Such Priorities Mechanisms are provided, for implementation in a data processing system having at least one physical processor and at least one associated cache memory, for allocating cache resources of the at least one cache memory to virtual processors of the data processing system. ... | 06/16/2011 |
| 20110138129 | CACHE MANAGEMENT FOR A NUMBER OF THREADS The illustrative embodiments provide a method, a computer program product, and an apparatus for managing a cache. A probability of a future request for data to be stored in a portion of the cache by a thread is identified for each of the number of threads to form a numb... | 06/09/2011 |
| 20110138131 | Probabilistic Offload Engine For Distributed Hierarchical Object Storage Devices A method and system having a probabilistic offload engine for distributed hierarchical object storage devices is disclosed. According to one embodiment, a system comprises a first storage system and a second storage system in communication with the first storage system.... | 06/09/2011 |
| 20110138130 | PROCESSOR AND METHOD OF CONTROL OF PROCESSOR A processor includes: a processing unit that has a first unit; a second unit that holds part of the data held by the first unit; a third unit that receives from the processing unit a first request including first attribute information for obtaining a first logical value... | 06/09/2011 |
| 20110131379 | PROCESSOR AND METHOD FOR WRITEBACK BUFFER REUSE A processor may include a writeback configured to perform a first writeback operation to store corresponding writeback data back to a lower-level memory upon eviction of the writeback data, and a writeback buffer configured to store the writeback data after the writebac... | 06/02/2011 |
| 20110119449 | APPLICATION INFORMATION CACHE A request for application information can be received from an application running in a process. The application information can be requested from an information repository, and received back from the repository in a first format. The application information can be conve... | 05/19/2011 |
| 20110113201 | GARBAGE COLLECTION IN A CACHE WITH REDUCED COMPLEXITY Garbage collection associated with a cache with reduced complexity. In an embodiment, a relative rank is computed for each cache item based on relative frequency of access and relative non-idle time of cache entry compared to other entries. Each item having a relative r... | 05/12/2011 |
| 20110099152 | ALTERNATE DATA STREAM CACHE FOR FILE CLASSIFICATION Described is caching classification-related metadata for a file in an alternate data stream of that file. When a file is classified (e.g., for data management), the classification properties are cached in association with the file, along with classification-related meta... | 04/28/2011 |
| 20110093654 | Memory control A data processing apparatus 1 comprises data processing circuitry 2, a memory 8 for storing data and a cache memory 5 for storing cached data from the memory 8. The cache memory 5 is partitioned into cache segments 12 whi... | 04/21/2011 |
| 20110093687 | MANAGING MULTIPLE SPECULATIVE ASSIST THREADS AT DIFFERING CACHE LEVELS An illustrative embodiment provides a computer-implemented process for managing multiple speculative assist threads for data pre-fetching that sends a command from an assist thread of a first processor to second processor and a memory, wherein parameters of the command ... | 04/21/2011 |
| 20110087844 | CONTENT NETWORK GLOBAL REPLACEMENT POLICY This invention is related to content delivery systems and methods. In one aspect of the invention, a content provider controls a replacement process operating at an edge server. The edge server services content providers and has a data store for storing content associat... | 04/14/2011 |
| 20110087845 | BURST-BASED CACHE DEAD BLOCK PREDICTION The present disclosure generally relates to cache memory systems and/or techniques to identify dead cache blocks in cache memory systems. Example systems may include a cache memory that is accessible by a cache client. The cache memory may include a plurality of storage... | 04/14/2011 |
