Class 711/131 - Multiport cache

Subclass of Class 711 - Electrical computers and digital processing systems: memory
Definition: Subject matter further comprising caches composed of multiport memory thereby allowing simultaneous reads
No. of applications: 27
Last issue date: 09/15/2011

Application No.	Application Title	Issue Date
20110225369	MULTIPORT DATA CACHE APPARATUS AND METHOD OF CONTROLLING THE SAME A multiport data cache apparatus and a method of controlling the same are provided. The multiport data cache apparatus includes a plurality of cache banks configured to share a cache line, and a data cache controller configured to receive cache requests for the cache ba...	09/15/2011
20110197013	CACHE SYSTEM A cache system includes a primary cache memory configured to input and output data between a computation unit, the primary cache memory includes multi-port memory units each including a storing unit that stores unit data having a first data size, a writing unit that sim...	08/11/2011
20110191543	Area and power efficient data coherency maintenance An apparatus for storing data that is being processed is disclosed. The apparatus comprises: a cache associated with a processor and for storing a local copy of data items stored in a memory for use by the processor, monitoring circuitry associated with the cache for mo...	08/04/2011
20110131377	MULTI-CORE PROCESSING CACHE IMAGE MANAGEMENT A multi-core processor chip comprises at least one shared cache having a plurality of ports and a plurality of address spaces and a plurality of processor cores. Each processor core is coupled to one of the plurality of ports such that each processor core is able to acc...	06/02/2011
20110119448	Data store maintenance requests in interconnects Interconnect circuitry for a data processing apparatus is disclosed. The interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device. The interconnect circuitry comprises: at least one inpu...	05/19/2011
20100011167	Heterogeneous processors sharing a common cache A multi-core processor providing heterogeneous processor cores and a shared cache is presented....	01/14/2010
20090228659	PROCESSOR AND COMPUTING SYSTEM A processor and a computing system are provided. A processor includes a processor core, and a buffer memory to read word data from a memory, the read word data including first byte data read by the processor core from the memory, and to store the read word data, wherein...	09/10/2009
20090177843	MICROPROCESSOR ARCHITECTURE HAVING ALTERNATIVE MEMORY ACCESS PATHS The present invention is directed to a system and method which employ two memory access paths: 1) a cache-access path in which block data is fetched from main memory for loading to a cache, and 2) a direct-access path in which individually-addressed data is fetched from...	07/09/2009
20090083491	Storage System and Associated Methods A storage system may include storage, a main pipeline to carry data for the storage, and a store pipeline to carry data for the storage. The storage system may also include a controller to prioritize data storage requests for the storage based upon available interleaves...	03/26/2009
20090019266	INFORMATION PROCESSING APPARATUS AND INFORMATION PROCESSING SYSTEM With respect to memory access instructions contained in an internal representation program, an information processing apparatus generates a load cache instruction, a cache hit judgment instruction, and a cache miss instruction that is executed in correspondence with a r...	01/15/2009
20090006760	Structure for Dual-Mode Memory Chip for High Capacity Memory Subsystem A design structure is provided for a dual-mode memory chip supporting a first operation mode in which received data access commands contain chip select data to identify the chip addressed by the command, and control logic in the memory chip determines whether the comman...	01/01/2009
20080276046	Architecture for a Multi-Port Cache Memory A multi-port cache memory (200) comprising a plurality of input ports (201, 203) for inputting a plurality of addresses, at least part of each address indexing a plurality of ways; a plurality of output ports (227, 299) for outputting data associate...	11/06/2008
20080256297	Multi-Port High-Level Cache Unit an a Method For Retrieving Information From a Multi-Port High-Level Cache Unit A device that includes multiple processors that are connected to multiple level-one cache units. The device also includes a multi-port high-level cache unit that includes a first modular interconnect, a second modular interconnect, multiple high-level cache paths; where...	10/16/2008
20080209129	Cache with High Access Store Bandwidth A cache memory system and method for supporting multiple simultaneous store operations using a plurality of tag memories is provided. The cache data system further provides a plurality of multiple simultaneous cache store functions along with a single cache load functio...	08/28/2008
20080168231	MEMORY WITH SHARED WRITE BIT LINE(S) A memory includes at least one write bit line and a plurality of memory cells. The at least one write bit line is configured to carry a write bit signal. The plurality of memory cells are arranged in a column and are configured to be selectively coupled to the at least ...	07/10/2008
20080040552	DUPLEX SYSTEM AND PROCESSOR SWITCHING METHOD The occurrence of a failure in any of an operational processor and a standby processor is monitored, and when a failure occurs in the operational processor, switching to the standby processor is made. A cache memory of each processor has a plurality of ports through whi...	02/14/2008
20080016282	Cache memory system A cache memory system includes: a plurality of cache lines, each including a data section for storing data of main memory and a line classification section for storing identification information that indicates whether the data stored in the data section is for instructi...	01/17/2008
20060212656	Dual storage apparatus and control method for the dual storage apparatus A dual storage apparatus is provided that comprises a first and a second memories for respectively retaining a set of identical data and a selector for selecting either of the two (2) sets of the data respectively read from the first and the second memory based on a rea...	09/21/2006
20060155953	Method and apparatus for accessing multiple vector elements in parallel Vector processing is a suitable technique for processing applications that have large computational demands. Vector processors provide high-level operations that work on vectors, i.e. linear arrays of numbers. Vector operations can be made faster than a sequence of scal...	07/13/2006
20060106989	Systems and methods for monitoring and controlling binary state devices using a memory device A static random access memory (SRAM) includes an input read register (IRR) for monitoring the state of external binary devices and an output drive register (ODR) for controlling the state of external binary devices. The SRAM can be a multi-port device for access by mult...	05/18/2006
20060101207	Multiport cache memory and access control system of multiport cache memory The multiport cache memory in which cache block data registered in an address array and a data array as components of the cache memory is indexed by a plurality of access addresses to simultaneously execute processing of reading target data corresponding to each of the ...	05/11/2006
20060069873	Instruction cache using single-ported memories Systems, methodologies, media, and other embodiments associated with cache systems are described. One exemplary system embodiment includes an instruction cache comprising single-ported memories. The example system can further include a cache control logic configured to ...	03/30/2006
20050268043	Reconfiguring logical settings in a storage system A storage system having multiple I/O interface ports is configured to detect a failed communication condition at a port. The storage system is configured to then attempt communication using a port configuration of another port that also exhibits a failed communication c...	12/01/2005
20050240733	Apparatus and method for selecting instructions for execution based on bank prediction of a multi-bank cache A processor having the capability to dispatch multiple parallel operations, including multiple load operations, accesses a cache which is divided into banks. Each bank supports a limited number of simultaneous read and write access operations. A bank prediction field is...	10/27/2005
20050102472	Data processor having cache memory A data processor has a first cache memory with a large capacity and one port and a second cache memory with a small capacity and two ports disposed between a main memory and an instruction processing section. Data which is frequently used is stored in the first cache me...	05/12/2005
20050071567	Modular register array An integrated circuit includes a register array having a number of entry groups. Each of the entry groups includes multiple entries. Each of the entries has multiple bits. The bits among different entries are grouped into bit groups. The integrated circuit also includes...	03/31/2005
20050005069	Integrated circuit memory devices having clock signal arbitration circuits therein and methods of performing clock signal arbitration A clock signal arbitration method includes arbitrating between first and second request signals generated in respective first and second clock domains that are asynchronously timed relative to each other, to obtain first arbitration results. These first arbitration resu...	01/06/2005

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Class 711/131 - Multiport cache