Did You Know...
...that the Eveready Battery began as an invention called the "electric flowerpot," which was a tube with a battery and light bulb inside? The idea was to fasten this gizmo to the side of a flowerpot so it would illuminate the flowers from the bottom. The idea died on the vine and the businessman who licensed the flower pot, Conrad Huber, was left with a pile of useless tubes -- until he found a way to market them as batteries to light the world!
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Application No. | Application Title | Issue Date |
| 20120110268 | DATA PROCESSING APPARATUS AND DATA PROCESSING METHOD The data processing apparatus according to an embodiment of the present invention includes: a first processor; a second processor; and an external RAM to/from which the first processor writes/reads data, the first processor including a cache memory for storing data used... | 05/03/2012 |
| 20120023295 | HYBRID ADDRESS MUTEX MECHANISM FOR MEMORY ACCESSES IN A NETWORK PROCESSOR Described embodiments provide arbitration for a cache of a network processor. Processing modules of the network processor generate memory access requests including a requested address and an ID value corresponding to the requesting processing module. Each request is eit... | 01/26/2012 |
| 20120011322 | METHOD AND APPARATUS FOR MANAGING MEMORY IN A MOBILE ELECTRONIC DEVICE According to embodiments described in the specification, a method and apparatus for managing memory in a mobile electronic device are provided. The method comprises: receiving a request to install an application; receiving at least one indication of data intended to be ... | 01/12/2012 |
| 20120005431 | Network with Distributed Shared Memory A computer network with distributed shared memory, including a clustered memory cache aggregated from and comprised of physical memory locations on a plurality of physically distinct computing systems. The clustered memory cache is accessible by a plurality of clients o... | 01/05/2012 |
| 20120005430 | STORAGE SYSTEM AND OWNERSHIP CONTROL METHOD FOR STORAGE SYSTEM Access to various types of resources is controlled efficiently, thereby enhancing the throughput. A storage system includes: a disk device for providing a volume for storing data to a host system; a channel adapter for writing data from the host system to the disk devic... | 01/05/2012 |
| 20110320694 | CACHED LATENCY REDUCTION UTILIZING EARLY ACCESS TO A SHARED PIPELINE A method of performing operations in a shared cache coupled to a first requestor and a second requestor includes receiving at the shared cache a first request from the second requester; assigning the request to a state machine; transmitting a first pipe pass request fro... | 12/29/2011 |
| 20110320727 | DYNAMIC CACHE QUEUE ALLOCATION BASED ON DESTINATION AVAILABILITY An apparatus for controlling operation of a cache includes a first command queue, a second command queue and an input controller configured to receive requests having a first command type and a second command type and to assign a first request having the first command t... | 12/29/2011 |
| 20110320729 | CACHE BANK MODELING WITH VARIABLE ACCESS AND BUSY TIMES Various embodiments of the present invention manage access to a cache memory. In one embodiment, a set of cache bank availability vectors are generated based on a current set of cache access requests currently operating on a set of cache banks and at least a variable bu... | 12/29/2011 |
| 20110320720 | Cache Line Replacement In A Symmetric Multiprocessing Computer Cache line replacement in a symmetric multiprocessing computer, the computer having a plurality of processors, a main memory that is shared among the processors, a plurality of cache levels including at least one high level of private caches and a low level shared cache... | 12/29/2011 |
| 20110320728 | PERFORMANCE OPTIMIZATION AND DYNAMIC RESOURCE RESERVATION FOR GUARANTEED COHERENCY UPDATES IN A MULTI-LEVEL CACHE HIERARCHY A cache includes a cache pipeline, a request receiver configured to receive off chip coherency requests from an off chip cache and a plurality of state machines coupled to the request receiver. The cache also includes an arbiter coupled between the plurality of state ma... | 12/29/2011 |
| 20110320695 | MITIGATING BUSY TIME IN A HIGH PERFORMANCE CACHE Various embodiments of the present invention mitigate busy time in a hierarchical store-through memory cache structure. In one embodiment, a cache directory associated with a memory cache is divided into a plurality of portions each associated with a portion memory cach... | 12/29/2011 |
| 20110320726 | STORAGE APPARATUS AND METHOD FOR CONTROLLING STORAGE APPARATUS A storage apparatus has a channel board 11; a drive board 13; a cache memory 14; a plurality of processor boards 12 that transfer data; and a shared memory 15. The channel board 11 stores a frame transfer table 521 contai... | 12/29/2011 |
| 20110314227 | Horizontal Cache Persistence In A Multi-Compute Node, Symmetric Multiprocessing Computer Horizontal cache persistence in a multi-compute node, SMP computer, including, responsive to a determination to evict a cache line on a first one of the compute nodes, broadcasting by a first compute node an eviction notice for the cache line; transmitting the state of ... | 12/22/2011 |
| 20110314212 | MANAGING IN-LINE STORE THROUGHPUT REDUCTION Various embodiments of the present invention manage a hierarchical store-through memory cache structure. A store request queue is associated with a processing core in multiple processing cores. At least one blocking condition is determined to have occurred at the store ... | 12/22/2011 |
| 20110307665 | PERSISTENT MEMORY FOR PROCESSOR MAIN MEMORY Subject matter disclosed herein relates to a system of one or more processors that includes persistent memory.... | 12/15/2011 |
| 20110296113 | RECOVERY IN SHARED MEMORY ENVIRONMENT A method, system, and computer usable program product for recovery in a shared memory environment are provided in the illustrative embodiments. A core in a multi-core processor is designated as a user level core (ULC), which executes an instruction to modify a memory wh... | 12/01/2011 |
| 20110293097 | VIRTUAL MACHINE MEMORY COMPARTMENTALIZATION IN MULTI-CORE ARCHITECTURES Techniques for memory compartmentalization for trusted execution of a virtual machine (VM) on a multi-core processing architecture are described. Memory compartmentalization may be achieved by encrypting layer 3 (L3) cache lines using a key under the control of a given ... | 12/01/2011 |
| 20110296407 | EXPOSURE OF VIRTUAL CACHE TOPOLOGY TO A GUEST OPERATING SYSTEM In a virtual machine environment, a hypervisor is configured to expose a virtual cache topology to a guest operating system, such that the virtual cache topology may be provided by corresponding physical cache topology. The virtual cache topology may be determined by th... | 12/01/2011 |
| 20110296406 | HYPERVISOR SCHEDULER Techniques for configuring a hypervisor scheduler to make use of cache topology of processors and physical memory distances between NUMA nodes when making scheduling decisions. In the same or other embodiments the hypervisor scheduler can be configured to optimize the s... | 12/01/2011 |
| 20110246721 | METHOD AND APPARATUS FOR PROVIDING AUTOMATIC SYNCHRONIZATION APPLIANCE A method and apparatus for data backup are disclosed. Embodiments of the method comprise receiving a set of data from a local computer, caching the received data locally on the storage appliance in a buffer module, uploading the cached data to a remote computer, and acc... | 10/06/2011 |
| 20110219191 | READER SET ENCODING FOR DIRECTORY OF SHARED CACHE MEMORY IN MULTIPROCESSOR SYSTEM In a parallel processing system with speculative execution, conflict checking occurs in a directory lookup of a cache memory that is shared by all processors. In each case, the same physical memory address will map to the same set of that cache, no matter which processo... | 09/08/2011 |
| 20110208916 | SHARED CACHE CONTROLLER, SHARED CACHE CONTROL METHOD AND INTEGRATED CIRCUIT A monitoring section 139 monitors a power control command for controlling power supplied to a processor for operating a plurality of operating systems or a plurality of processors. A cache entry selecting section 141 sets a cache entry used by the operatin... | 08/25/2011 |
| 20110197031 | Update Handler For Multi-Channel Cache Disclosed herein is a miss handler for a multi-channel cache memory, and a method that includes determining a need to update a multi-channel cache memory due at least to one of an occurrence of a cache miss or a data prefetch being needed. The method further includes op... | 08/11/2011 |
| 20110191542 | SYSTEM-WIDE QUIESCENCE AND PER-THREAD TRANSACTION FENCE IN A DISTRIBUTED CACHING AGENT Methods and apparatus relating to system-wide quiescence and per-thread transaction fence in a distributed caching agent are described. Some embodiments utilize messages, counters, and/or state machines that support system-wide quiescence and per-thread transaction fenc... | 08/04/2011 |
| 20110185117 | SYSTEMS AND METHODS FOR MANAGING A CACHE IN A MULTI-NODE VIRTUAL TAPE CONTROLLER According to one embodiment, a system includes a virtual tape library having a cache, a virtual tape controller (VTC) coupled to the virtual tape library, and an interface for coupling at least one host to the VTC. The cache is shared by all the hosts, and a common view... | 07/28/2011 |
| 20110185125 | RESOURCE SHARING TO REDUCE IMPLEMENTATION COSTS IN A MULTICORE PROCESSOR A processor may include several processor cores, each including a respective higher-level cache; a lower-level cache including several tag units each including several controllers, where each controller corresponds to a respective cache bank configured to store data, an... | 07/28/2011 |
| 20110185126 | MULTIPROCESSOR SYSTEM When a processor has transitioned to an operation stop state, it is possible to reduce the power consumption of a cache memory while maintaining the consistency of cache data. A multiprocessor system includes first and second processors, a shared memory, first and secon... | 07/28/2011 |
| 20110179416 | Virtual Machine Access to Storage Via a Multi-Queue IO Storage Adapter With Optimized Cache Affinity and PCPU Load Balancing A method is provided for use in a system that includes a host machine that includes multiple physical CPUs (PCPUs) and at least two cache nodes that are shared by different sets of the PCPUs, comprising: creating in a memory device multiple sets of lanes each lane set a... | 07/21/2011 |
| 20110161596 | DIRECTORY-BASED COHERENCE CACHING Techniques are generally described for methods, systems, data processing devices and computer readable media related to multi-core parallel processing directory-based cache coherence. Example systems may include one multi-core processor or multiple multi-core processors... | 06/30/2011 |
| 20110161630 | GENERAL PURPOSE HARDWARE TO REPLACE FAULTY CORE COMPONENTS THAT MAY ALSO PROVIDE ADDITIONAL PROCESSOR FUNCTIONALITY An apparatus and method is described herein for replacing faulty core components. General purpose hardware is provided to replace core pipeline components, such as execution units. In the embodiment of execution unit replacement, a proxy unit is provided, such that mapp... | 06/30/2011 |
| 20110161586 | Shared Memories for Energy Efficient Multi-Core Processors Technologies are described herein related to multi-core processors that are adapted to share processor resources. An example multi-core processor can include a plurality of processor cores. The multi-core processor further can include a shared register file selectively ... | 06/30/2011 |
| 20110161590 | SYNCHRONIZING ACCESS TO DATA IN SHARED MEMORY VIA UPPER LEVEL CACHE QUEUING A processing unit includes a store-in lower level cache having reservation logic that determines presence or absence of a reservation and a processor core including a store-through upper level cache, an instruction execution unit, a load unit that, responsive to a hit i... | 06/30/2011 |
| 20110153948 | SYSTEMS, METHODS, AND APPARATUS FOR MONITORING SYNCHRONIZATION IN A DISTRIBUTED CACHE Systems, apparatus, and method of monitoring synchronization in a distributed cache are described. In an exemplary embodiment, a first and second processing core process a first and second thread respectively. A first and second distributed cache slices store data for e... | 06/23/2011 |
| 20110154345 | Multicore Processor Including Two or More Collision Domain Networks Implementations and techniques for multicore processors having a domain interconnection network configured to associate a first collision domain network with a second collision domain network in communication are generally disclosed.... | 06/23/2011 |
| 20110145505 | Assigning Cache Priorities to Virtual/Logical Processors and Partitioning a Cache According to Such Priorities Mechanisms are provided, for implementation in a data processing system having at least one physical processor and at least one associated cache memory, for allocating cache resources of the at least one cache memory to virtual processors of the data processing system. ... | 06/16/2011 |
| 20110145506 | Replacing Cache Lines In A Cache Memory In one embodiment, the present invention includes a cache memory including cache lines that each have a tag field including a state portion to store a cache coherency state of data stored in the line and a weight portion to store a weight corresponding to a relative imp... | 06/16/2011 |
| 20110138128 | Technique for tracking shared data in a multi-core processor or multi-processor system A technique to track shared information in a multi-core processor or multi-processor system. In one embodiment, core identification information (“core IDs”) are used to track shared information among multiple cores in a multi-core processor or multiple processors in... | 06/09/2011 |
| 20110131377 | MULTI-CORE PROCESSING CACHE IMAGE MANAGEMENT A multi-core processor chip comprises at least one shared cache having a plurality of ports and a plurality of address spaces and a plurality of processor cores. Each processor core is coupled to one of the plurality of ports such that each processor core is able to acc... | 06/02/2011 |
| 20110125971 | Shared Upper Level Cache Architecture Various implementations of shared upper level cache architectures are disclosed.... | 05/26/2011 |
| 20110119446 | CONDITIONAL LOAD AND STORE IN A SHARED CACHE A method, system and computer program product are disclosed for implementing load-reserve and store-conditional instructions in a multi-processor computing system. The computing system includes a multitude of processor units and a shared memory cache, and each of the pr... | 05/19/2011 |
