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| Application No. | Application Title | Issue Date |
| 20120054442 | METHOD AND APPARATUS FOR ALLOCATING INSTRUCTION AND DATA FOR A UNIFIED CACHE The present invention provides a method and apparatus for allocating space in a unified cache. The method may include partitioning the unified cache into a first portion of lines that only store copies of instructions retrieved from a memory and a second portion of line... | 03/01/2012 |
| 20120042131 | Flexible use of extended cache using a partition cache footprint An approach is provided to identifying cache extension sizes that correspond to different partitions that are running on a computer system. The approach extends a first hardware cache associated with a first processing core that is included in the processor's silicon su... | 02/16/2012 |
| 20110320687 | REDUCING WRITE AMPLIFICATION IN A CACHE WITH FLASH MEMORY USED AS A WRITE CACHE Embodiments of the invention are directed to reducing write amplification in a cache with flash memory used as a write cache. An embodiment of the invention includes partitioning at least one flash memory device in the cache into a plurality of logical partitions. Each ... | 12/29/2011 |
| 20110314226 | SEMICONDUCTOR STORAGE DEVICE BASED CACHE MANAGER In general, the present invention relates to semiconductor storage systems (SSDs). Specifically, the present invention relates to SSD based cache manager. In a typical embodiment, a cache balancer is coupled to a set of cache meta data units. A set of cache algorithms t... | 12/22/2011 |
| 20110185127 | PROCESSOR CIRCUIT WITH SHARED MEMORY AND BUFFER SYSTEM The processor circuit (1) has a Harvard architecture. This processor circuit includes a calculation unit (2), a first memory element (3a) for data storage and a second memory element (4a) for instruction storage. Said first and ... | 07/28/2011 |
| 20110161557 | DISTRIBUTED MEDIA CACHE FOR DATA STORAGE SYSTEMS This disclosure is related to distributed media cache for data storage systems, such as disc drives, flash devices, or hybrid devices. In one example, a data storage device comprises a data storage medium and a controller adapted to selectively divide a media cache into... | 06/30/2011 |
| 20110145504 | Independently Controllable And Reconfigurable Virtual Memory Devices In Memory Modules That Are Pin-compatible With Standard Memory Modules Various embodiments of the present invention are directed multi-core memory modules. In one embodiment, a memory module (500) includes memory chips, and a demultiplexer register (502) electronically connected to each of the memory chips and a memory contro... | 06/16/2011 |
| 20110145493 | Independently Controlled Virtual Memory Devices In Memory Modules Various embodiments of the present invention are directed a multi-core memory modules. In one embodiment, a memory module (500) includes at least one virtual memory device and a demultiplexer register (502) disposed between the at least one virtual memory ... | 06/16/2011 |
| 20110131378 | Managing Access to a Cache Memory Managing access to a cache memory includes dividing said cache memory into multiple of cache areas, each cache area having multiple entries; and providing at least one separate lock attribute for each cache area such that only a processor thread having possession of the... | 06/02/2011 |
| 20110107033 | METHOD AND APPARATUS FOR PROVIDING AN APPLICATION-LEVEL CACHE An approach is provided for providing an application-level cache. A caching application configures at least one memory of a mobile terminal into an application-level cache with a locked region and a floating region. The caching application then causes, at least in part,... | 05/05/2011 |
| 20110087843 | Monitoring cache usage in a distributed shared cache An apparatus, method, and system are disclosed. In one embodiment the apparatus includes a cache memory, which a number of sets. Each of the sets in the cache memory have several cache lines. The apparatus also includes at least one process resource table. The process r... | 04/14/2011 |
| 20110055827 | Cache Partitioning in Virtualized Environments A mechanism is provided in a virtual machine monitor for providing cache partitioning in virtualized environments. The mechanism assigns a virtual identification (ID) to each virtual machine in the virtualized environment. The processing core stores the virtual ID of th... | 03/03/2011 |
| 20110040940 | Dynamic cache sharing based on power state The present invention discloses a method comprising: sending cache request; monitoring power state; comparing said power state; allocating cache resources; filling cache; updating said power state; repeating said sending, said monitoring, said comparing, said allocating... | 02/17/2011 |
| 20110010504 | Combined Transparent/Non-Transparent Cache In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a corresponding tag memory. The non-transparent portion may be software controlled... | 01/13/2011 |
| 20100332762 | DIRECTORY CACHE ALLOCATION BASED ON SNOOP RESPONSE INFORMATION Methods and apparatus relating to directory cache allocation that is based on snoop response information are described. In one embodiment, an entry in a directory cache may be allocated for an address in response to a determination that another caching agent has a copy ... | 12/30/2010 |
| 20100332761 | Reconfigurable Cache A mechanism is provided for providing an improved reconfigurable cache. The mechanism partitions a large cache into inclusive cache regions with equal-ratio size or other coarse size increase. The cache controller includes an address decoder for the large cache with a l... | 12/30/2010 |
| 20100318742 | Partitioned Replacement For Cache Memory In a particular embodiment, a circuit device includes a translation look-aside buffer (TLB) configured to receive a virtual address and to translate the virtual address to a physical address of a cache having at least two partitions. The circuit device also includes a c... | 12/16/2010 |
| 20100318744 | DIFFERENTIAL CACHING MECHANISM BASED ON MEDIA I/O SPEED A method for allocating space in a cache based on media I/O speed is disclosed herein. In certain embodiments, such a method may include storing, in a read cache, cache entries associated with faster-responding storage devices and cache entries associated with slower-re... | 12/16/2010 |
| 20100312967 | CACHE CONTROL APPARATUS AND METHOD A cache control apparatus is provided in a computer system including an access source and a storage apparatus. This device, based on I/O status information, which is information denoting the I/O status in accordance with an I/O command from the access source, determines... | 12/09/2010 |
| 20100302077 | WEAR REDUCTION METHODS BY USING COMPRESSION/DECOMPRESSION TECHNIQUES WITH FAST RANDOM ACCESS The present invention reduces the number of writes to a main memory to increase useful life of the main memory. To reduce the number of writes to the main memory, data to be written is written to a cache line in a lowest-level cache memory and in a higher-level cache me... | 12/02/2010 |
| 20100293334 | LOCATION UPDATES FOR A DISTRIBUTED DATA STORE Version indicators within an existing range can be associated with a data partition in a distributed data store. A partition reconfiguration can be associated with one of multiple partitions in the data store, and a new version indicator that is outside the existing ran... | 11/18/2010 |
| 20100293332 | CACHE ENUMERATION AND INDEXING In response to a request including a state object, which can indicate a state of an enumeration of a cache, the enumeration can be continued by using the state object to identify and send cache data. Also, an enumeration of cache units can be performed by traversing a d... | 11/18/2010 |
| 20100268889 | COMPILER BASED CACHE ALLOCATION Techniques a generally described for creating a compiler determined map for the allocation of memory space within a cache. An example computing system is disclosed having a multicore processor with a plurality of processor cores. At least one cache may be accessible to ... | 10/21/2010 |
| 20100235580 | Multi-Domain Management of a Cache in a Processor System A system and method are provided for managing cache memory in a computer system. A cache controller portions a cache memory into a plurality of partitions, where each partition includes a plurality of physical cache addresses. Then, the method accepts a memory access me... | 09/16/2010 |
| 20100191915 | SYSTEM AND COMPUTER PROGRAM PRODUCT FOR DYNAMIC QUEUE SPLITTING FOR MAXIMIZING THROUGHPUT OF QUEUE BASED OPERATIONS WHILE MAINTAINING PER-DESTINATION ORDER OF OPERATIONS A system for providing dynamic queue splitting to maximize throughput of queue entry processing while maintaining the order of queued operations on a per-destination basis. Multiple queues are dynamically created by splitting heavily loaded queues in two. As queues beco... | 07/29/2010 |
| 20100179865 | MULTIMEDIA CONTENT CACHE Music can be broadcast from a radio station and recorded onto a cache of a personal electronic device, such as a portable digital music player. The recording can occur such that there is segmenting of music into different cache portions based upon classification. Instea... | 07/15/2010 |
| 20100174863 | SYSTEM FOR PROVIDING SCALABLE IN-MEMORY CACHING FOR A DISTRIBUTED DATABASE A system is described for providing scalable in-memory caching for a distributed database. The system may include a cache, an interface, a non-volatile memory and a processor. The cache may store a cached copy of data items stored in the non-volatile memory. The interfa... | 07/08/2010 |
| 20100131715 | Updating Data within a Business Planning Tool A apparatus is provided for updating data within a business planning tool. The apparatus comprises a computer memory (22) arranged to store operational data in a plurality of line items (50), each line item (50) being arranged to represent operation... | 05/27/2010 |
| 20100122032 | SELECTIVELY PERFORMING LOOKUPS FOR CACHE LINES Embodiments of the present invention provide a system that selectively performs lookups for cache lines. During operation, the system by maintains a lower-level cache and a higher-level cache in accordance with a set of rules that dictate conditions under which cache li... | 05/13/2010 |
| 20100082906 | Apparatus and method for low touch cache management In some embodiments, a processor-based system includes a processor, a system memory coupled to the processor, a mass storage device, a cache memory located between the system memory and the mass storage device, and code stored on the processor-based system to cause the ... | 04/01/2010 |
| 20100077151 | HARDWARE TRIGGERED DATA CACHE LINE PRE-ALLOCATION A computer system includes a data cache supported by a copy-back buffer and pre-allocation request stack. A programmable trigger mechanism inspects each store operation made by the processor to the data cache to see if a next cache line should be pre-allocated. If the s... | 03/25/2010 |
| 20100070715 | APPARATUS, SYSTEM AND METHOD FOR STORAGE CACHE DEDUPLICATION An apparatus, system, and method are disclosed for deduplicating storage cache data. A storage cache partition table has at least one entry associating a specified storage address range with one or more specified storage partitions. A deduplication module creates an ent... | 03/18/2010 |
| 20100030971 | CACHE SYSTEM, CACHE SYSTEM CONTROL METHOD, AND INFORMATION PROCESSING APPARATUS To provide a cache system that can dynamically change a cache capacity by memory areas divided into plural. The cache system includes a line counter that counts the number of effective lines for each memory area. The effective line is a cache line in which effective cac... | 02/04/2010 |
| 20100017568 | Cache Used Both as Cache and Staging Buffer In one embodiment, a cache comprises a data memory comprising a plurality of data entries, each data entry having capacity to store a cache block of data, and a cache control unit coupled to the data memory. The cache control unit is configured to dynamically allocate a... | 01/21/2010 |
| 20090328022 | SYSTEMS AND METHODS FOR MAINTAINING CRTM CODE Systems, methods and media for updating CRTM code in a computing machine are disclosed. In one embodiment, the CRTM code initially resides in ROM and updated CRTM is stored in a staging area of the ROM. A logical partition of L2 cache may be created to store a heap and ... | 12/31/2009 |
| 20090313437 | METHOD AND SYSTEM OF OPTIMAL CACHE PARTITIONING IN IPTV NETWORKS In an IPTV network, one or more caches may be provided at the network nodes for storing video content in order to reduce bandwidth requirements. Cache functions such as cache effectiveness and cacheability may be defined and optimized to determine optimal partitioning o... | 12/17/2009 |
| 20090313436 | CACHE REGIONS A cache region can be created in a cache in response to receiving a cache region creation request from an application. A storage request from the application can identify the cache region and one or more objects to be stored in the cache region. Those objects can be sto... | 12/17/2009 |
| 20090292880 | CACHE MEMORY SYSTEM A cache memory system controlled by an arbiter includes a memory unit having a cache memory whose capacity is changeable, and an invalidation processing unit that requests invalidation of data stored at a position where invalidation is performed when the capacity of the... | 11/26/2009 |
| 20090271573 | PARTITIONED MANAGEMENT DATA CACHE A system and method for decreasing system management data access time. A system includes a device, a cache memory coupled to the device, and a cache memory refresh controller. The device provides system management information. The cache memory stores system management i... | 10/29/2009 |
| 20090248986 | Apparatus for and Method of Implementing Multiple Content Based Data Caches A novel and useful mechanism enabling the partitioning of a normally shared L1 data cache into several different independent caches, wherein each cache is dedicated to a specific data type. To further optimize performance each individual L1 data cache is placed in relat... | 10/01/2009 |
