Did You Know...
...that after Parker Brothers executives turned down the game of Monopoly because it had "52 fundamental errors" (including taking too long to play), a copy of the game wound up in the home of the company president who stayed up until 1 a.m. to finish playing it? He was so impressed by the game that the next day he wrote to inventor Charles Darrow and offered to buy it!
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| Application No. | Application Title | Issue Date |
| 20110320725 | DYNAMIC MODE TRANSITIONS FOR CACHE INSTRUCTIONS A method of providing requests to a cache pipeline includes receiving a plurality of requests from one or more state machines at an arbiter, selecting one of the plurality of requests as a selected request, the selected request having been provided by a first state mach... | 12/29/2011 |
| 20110320697 | DYNAMICALLY SUPPORTING VARIABLE CACHE ARRAY BUSY AND ACCESS TIMES Various embodiments of the present invention manage access to a cache memory. In or more embodiments a request for a targeted interleave within a cache memory is received. The request is associated with an operation of a given type. The target is determined to be availa... | 12/29/2011 |
| 20100191893 | Dual Access for Single Port Cache A method and system for accessing a single port multi-way cache includes an address multiplexer that simultaneously addresses a set of data and a set of program instructions in the multi-way cache. Duplicate output way multiplexers respectively select data and program i... | 07/29/2010 |
| 20100088460 | MEMORY APPARATUS, SYSTEMS, AND METHODS Memory requests for information from a processor are received in an interface device, and the interface device is coupled to a stack including two or more memory devices. The interface device is operated to select a memory device from a number of memory devices includin... | 04/08/2010 |
| 20100037024 | MEMORY INTERLEAVE FOR HETEROGENEOUS COMPUTING A memory interleave system for providing memory interleave for a heterogeneous computing system is provided. The memory interleave system effectively interleaves memory that is accessed by heterogeneous compute elements in different ways, such as via cache-block accesse... | 02/11/2010 |
| 20090172286 | Method And System For Balancing Host Write Operations And Cache Flushing A method and system for balancing host write operations and cache flushing is disclosed. The method may include steps of determining an available capacity in a cache storage portion of a self-caching storage device, determining a ratio of cache flushing steps to host wr... | 07/02/2009 |
| 20080301370 | Memory Module A memory module includes a module circuit board, an amplifier circuit disposed on the module circuit board for amplifying an input signal, and a memory component to store a data item, wherein the memory component is disposed on the module circuit board. The amplifier ci... | 12/04/2008 |
| 20080120466 | DUAL ACCESS FOR SINGLE PORT CACHE A method and system for accessing a single port multi-way cache includes an address multiplexer that simultaneously addresses a set of data and a set of program instructions in the multi-way cache. Duplicate output way multiplexers respectively select data and program i... | 05/22/2008 |
| 20060149903 | Fault tolerant computer system and a synchronization method for the same Each time a sync controller sequentially issues a read request to a memory controller, a count value of a first counter is incremented. When a read operation is conducted for the read request, a count value of a second counter is incremented and the data is transferred ... | 07/06/2006 |
