Did You Know...
...that a workman who left the soap mixing machine on too long was responsible for making Ivory Soap? He was so embarrassed by his mistake that he threw the mess in a stream. Imagine his dismay when the evidence of his error floated to the surface! Result: Ivory soap, the soap that floats.
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| Application No. | Application Title | Issue Date |
| 20120131265 | WRITE CACHE STRUCTURE IN A STORAGE SYSTEM A method of writing data units to a storage device. The data units are cached in a first level cache sorted by logical address. A group (Gj) of sorted data units is transferred from the first level cache to a second level cache embodied in a solid state memor... | 05/24/2012 |
| 20120110266 | DISABLING CACHE PORTIONS DURING LOW VOLTAGE OPERATIONS Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at... | 05/03/2012 |
| 20120084511 | INEFFECTIVE PREFETCH DETERMINATION AND LATENCY OPTIMIZATION A processor of an information handling system (IHS) initiates an L3 cache prefetch operation in response to a demand load during instruction processing. The processor selects an L3 cache prefetch at random for tracking as a target prefetched instruction. The processor i... | 04/05/2012 |
| 20120072668 | SLOT/SUB-SLOT PREFETCH ARCHITECTURE FOR MULTIPLE MEMORY REQUESTORS A prefetch unit generates a prefetch address in response to an address associated with a memory read request received from the first or second cache. The prefetch unit includes a prefetch buffer that is arranged to store the prefetch address in an address buffer of a se... | 03/22/2012 |
| 20120072667 | VARIABLE LINE SIZE PREFETCHER FOR MULTIPLE MEMORY REQUESTORS A prefetch unit generates prefetch addresses in response to an initial received memory read request, an address associated with the initial received memory read request, a line length of the requestor of the initial received memory read request, and a request type width... | 03/22/2012 |
| 20120054439 | METHOD AND APPARATUS FOR ALLOCATING CACHE BANDWIDTH TO MULTIPLE PROCESSORS The present invention provides a method and apparatus for allocating cache bandwidth to multiple processors. One embodiment of the method includes delaying, at a local device associated with a local cache, a first cache probe from a non-local device to the local cache f... | 03/01/2012 |
| 20120054440 | SYSTEMS AND METHODS FOR PROVIDING A HIERARCHY OF CACHE LAYERS OF DIFFERENT TYPES FOR INTEXT ADVERTISING The present invention is related to a method for determining duplicate clicks via a multi-layered cache. The method includes establishing, by a cache manager executing on a device, a cache comprising a hierarchy of a plurality of cache layers. The cache manager may esta... | 03/01/2012 |
| 20120042126 | METHOD FOR CONCURRENT FLUSH OF L1 AND L2 CACHES The present invention provides a method and apparatus for use with a hierarchical cache system. The method may include concurrently flushing one or more first caches and a second cache of a multi-level cache. Each first cache is smaller and at a lower level in the multi... | 02/16/2012 |
| 20120042127 | CACHE PARTITIONING A method and apparatus for partitioning a cache includes determining an allocation of a subcache out of a plurality of subcaches within the cache for association with a compute unit out of a plurality of compute units. Data is processed by the compute unit, and the comp... | 02/16/2012 |
| 20120030429 | METHOD FOR COORDINATING UPDATES TO DATABASE AND IN-MEMORY CACHE A computer method and system of caching. In a multi-threaded application, different threads execute respective transactions accessing a data store (e.g. database) from a single server. The method and system represent status of datastore transactions using respective cer... | 02/02/2012 |
| 20120030428 | INFORMATION PROCESSING DEVICE, MEMORY MANAGEMENT DEVICE AND MEMORY MANAGEMENT METHOD According to one embodiment, an information processing device includes a first determination section and a setting section. The first determination section determines inconsistency between first data and second data. The first data is stored in a nonvolatile semiconduct... | 02/02/2012 |
| 20120017049 | METHOD AND APPARATUS FOR IMPLEMENTING CACHE COHERENCY OF A PROCESSOR An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging ne... | 01/19/2012 |
| 20110320701 | OPTIMIZING EDRAM REFRESH RATES IN A HIGH PERFORMANCE CACHE ARCHITECTURE Optimizing refresh request transmission rates in a high performance cache comprising: a refresh requestor configured to transmit a refresh request to a cache memory at a first refresh rate, the first refresh rate comprising an interval, the interval comprising receiving... | 12/29/2011 |
| 20110320694 | CACHED LATENCY REDUCTION UTILIZING EARLY ACCESS TO A SHARED PIPELINE A method of performing operations in a shared cache coupled to a first requestor and a second requestor includes receiving at the shared cache a first request from the second requester; assigning the request to a state machine; transmitting a first pipe pass request fro... | 12/29/2011 |
| 20110320720 | Cache Line Replacement In A Symmetric Multiprocessing Computer Cache line replacement in a symmetric multiprocessing computer, the computer having a plurality of processors, a main memory that is shared among the processors, a plurality of cache levels including at least one high level of private caches and a low level shared cache... | 12/29/2011 |
| 20110320721 | DYNAMIC TRAILING EDGE LATENCY ABSORPTION FOR FETCH DATA FORWARDED FROM A SHARED DATA/CONTROL INTERFACE A computer-implemented method for managing data transfer in a multi-level memory hierarchy that includes receiving a fetch request for allocation of data in a higher level memory, determining whether a data bus between the higher level memory and a lower level memory is... | 12/29/2011 |
| 20110302561 | ARCHITECTURE-AWARE FIELD AFFINITY ESTIMATION A data layout optimization may utilize affinity estimation between paris of fields of a record in a computer program. The affinity estimation may be determined based on a trace of an execution and in view of actual processing entities performing each access to the field... | 12/08/2011 |
| 20110302372 | SMT/ECO MODE BASED ON CACHE MISS RATE A computer implemented method for managing an execution mode for a parallel processor is provided. A monitor identifies a first efficiency rate for a first contested resource of the parallel processor operating in a first operating mode. Responsive to identifying the fi... | 12/08/2011 |
| 20110296093 | PROGRAM AND SENSE OPERATIONS IN A NON-VOLATILE MEMORY DEVICE Methods for programming and sensing in a memory device, a data cache, and a memory device are disclosed. In one such method, all of the bit lines of a memory block are programmed or sensed during the same program or sense operation by alternately multiplexing the odd or... | 12/01/2011 |
| 20110289276 | CACHE MEMORY APPARATUS A cache memory apparatus includes an L1 cache memory, an L2 cache memory coupled to the L1 cache memory, an arithmetic logic unit (ALU) within the L2 cache memory, the combined ALU and L2 cache memory being configured to perform therewithin at least one of: an arithmeti... | 11/24/2011 |
| 20110276762 | COORDINATED WRITEBACK OF DIRTY CACHELINES A data processing system includes a processor core and a cache memory hierarchy coupled to the processor core. The cache memory hierarchy includes at least one upper level cache and a lowest level cache. A memory controller is coupled to the lowest level cache and to a ... | 11/10/2011 |
| 20110276763 | MEMORY BUS WRITE PRIORITIZATION A data processing system includes a multi-level cache hierarchy including a lowest level cache, a processor core coupled to the multi-level cache hierarchy, and a memory controller coupled to the lowest level cache and to a memory bus of a system memory. The memory cont... | 11/10/2011 |
| 20110271057 | CACHE ACCESS FILTERING FOR PROCESSORS WITHOUT SECONDARY MISS DETECTION The disclosed embodiments provide a system that filters duplicate requests from an L1 cache for a cache line. During operation, the system receives at an L2 cache a first request and a second request for the same cache line, and stores identifying informat... | 11/03/2011 |
| 20110264860 | MULTI-MODAL DATA PREFETCHER A microprocessor includes first and second cache memories occupying distinct hierarchy levels, the second backing the first. A prefetcher monitors load operations and maintains a recent history of the load operations from a cache line and determines whether the recent h... | 10/27/2011 |
| 20110264861 | METHODS AND SYSTEMS FOR UTILIZING BYTECODE IN AN ON-DEMAND SERVICE ENVIRONMENT INCLUDING PROVIDING MULTI-TENANT RUNTIME ENVIRONMENTS AND SYSTEMS Execution of code in a multitenant runtime environment. A request to execute code corresponding to a tenant identifier (ID) is received in a multitenant environment. The multitenant database stores data for multiple client entities each identified by a tenant ID having ... | 10/27/2011 |
| 20110219190 | CACHE WITH RELOAD CAPABILITY AFTER POWER RESTORATION A method and apparatus for repopulating a cache are disclosed. At least a portion of the contents of the cache are stored in a location separate from the cache. Power is removed from the cache and is restored some time later. After power has been restored to the cache, ... | 09/08/2011 |
| 20110213947 | System and Method for Power Optimization A technique for reducing the power consumption required to execute processing operations. A processing complex, such as a CPU or a GPU, includes a first set of cores comprising one or more fast cores and second set of cores comprising one or more slow cores. A processin... | 09/01/2011 |
| 20110208915 | Fused Store Exclusive/Memory Barrier Operation In an embodiment, a processor may be configured to detect a store exclusive operation followed by a memory barrier operation in a speculative instruction stream being executed by the processor. The processor may fuse the store exclusive operation and the memory barrier ... | 08/25/2011 |
| 20110202727 | Apparatus and Methods to Reduce Duplicate Line Fills in a Victim Cache Techniques and methods are used to reduce allocations to a higher level cache of cache lines displaced from a lower level cache. The allocations of the displaced cache lines are prevented for displaced cache lines that are determined to be redundant in the next level ca... | 08/18/2011 |
| 20110202726 | Apparatus and method for handling data in a cache A data processing apparatus for forming a portion of a coherent cache system comprises at least one master device for performing data processing operations, and a cache coupled to the at least one master device and arranged to store data values for access by that at lea... | 08/18/2011 |
| 20110197030 | Latency Reduction for Cache Coherent Bus-Based Cache In one embodiment, a system comprises a plurality of agents coupled to an interconnect and a cache coupled to the interconnect. The plurality of agents are configured to cache data. A first agent of the plurality of agents is configured to initiate a transaction on the ... | 08/11/2011 |
| 20110185125 | RESOURCE SHARING TO REDUCE IMPLEMENTATION COSTS IN A MULTICORE PROCESSOR A processor may include several processor cores, each including a respective higher-level cache; a lower-level cache including several tag units each including several controllers, where each controller corresponds to a respective cache bank configured to store data, an... | 07/28/2011 |
| 20110173391 | System and Method to Access a Portion of a Level Two Memory and a Level One Memory A system and method to access data from a portion of a level two memory or from a level one memory is disclosed. In a particular embodiment, the system includes a level one cache and a level two memory. A first portion of the level two memory is coupled to an input port... | 07/14/2011 |
| 20110173393 | CACHE MEMORY, MEMORY SYSTEM, AND CONTROL METHOD THEREFOR A cache memory according to the present invention includes: a first port for input of a command from the processor; a second port for input of a command from a master other than the processor; a hit determining unit which, when a command is input to said first port or s... | 07/14/2011 |
| 20110173392 | EVICT ON WRITE, A MANAGEMENT STRATEGY FOR A PREFETCH UNIT AND/OR FIRST LEVEL CACHE IN A MULTIPROCESSOR SYSTEM WITH SPECULATIVE EXECUTION In a multiprocessor system with at least two levels of cache, a speculative thread may run on a core processor in parallel with other threads. When the thread seeks to do a write to main memory, this access is to be written through the first level cache to the second le... | 07/14/2011 |
| 20110167224 | CACHE MEMORY, MEMORY SYSTEM, DATA COPYING METHOD, AND DATA REWRITING METHOD A cache memory according to an aspect of the present invention including entries each of which includes a tag address, line data, and a dirty flag, the cache memory includes: a command execution unit which rewrites, when a first command is instructed by a processor, a t... | 07/07/2011 |
| 20110161588 | FORMATION OF AN EXCLUSIVE OWNERSHIP COHERENCE STATE IN A LOWER LEVEL CACHE In response to a memory access request of a processor core that targets a target cache line, the lower level cache of a vertical cache hierarchy associated with the processor core supplies a copy of the target cache line to an upper level cache in the vertical cache hie... | 06/30/2011 |
| 20110161591 | INCREASED NAND FLASH MEMORY READ THROUGHPUT A method of reading sequential pages of flash memory from alternating memory blocks comprises loading data from a first page into a first primary data cache and a second page into a second primary data cache simultaneously, the first and second pages loaded from differe... | 06/30/2011 |
| 20110161585 | PROCESSING NON-OWNERSHIP LOAD REQUESTS HITTING MODIFIED LINE IN CACHE OF A DIFFERENT PROCESSOR Methods and apparatus to efficiently process non-ownership load requests hitting modified line (M-line) in cache of a different processor are described. In one embodiment, a first agent changes the state of a first data and forwards it to a second, requesting agent who ... | 06/30/2011 |
| 20110161575 | MICROCODE REFACTORING AND CACHING Methods and apparatus relating to microcode refactoring and/or caching are described. In some embodiments, an off-chip structure that stores microcode is shared by multiple processor cores. Other embodiments are also described and claimed.... | 06/30/2011 |
