Celebrity Inventors
Comic actor Danny Kaye received patent D166,807 for the co-design of "Blowout Toy or the Like". It's similar to one of those toys that unravels when you blow into at a birthday party except Kaye's has three blowouts going in different directions, not just one.
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| Application No. | Application Title | Issue Date |
| 20120110367 | Architecture and Method for Eliminating Store Buffers in a DSP/Processor with Multiple Memory Accesses A method and apparatus for controlling system access to a memory that includes receiving first and second instructions, and evaluating whether both instructions can architecturally complete. When at least one instruction cannot architecturally complete, delaying both in... | 05/03/2012 |
| 20120084510 | Computing Machine and Computing System According to one embodiment, a computing machine includes a virtual machine operated on a virtual machine monitor, the computing machine includes a first memory device, and a second memory device. The virtual machine monitor is configured to assign a part of a region of... | 04/05/2012 |
| 20110314225 | COMPUTATIONAL RESOURCE ASSIGNMENT DEVICE, COMPUTATIONAL RESOURCE ASSIGNMENT METHOD AND COMPUTATIONAL RESOURCE ASSIGNMENT PROGRAM In a multi-core processor system, cache memories are provided respectively for a plurality of processors. An assignment management unit manages assignment of tasks to the processors. A cache status calculation unit calculates a cache usage status such as a memory access... | 12/22/2011 |
| 20110271056 | MULTITHREADED CLUSTERED MICROARCHITECTURE WITH DYNAMIC BACK-END ASSIGNMENT A multithreaded clustered microarchitecture with dynamic back-end assignment is presented. A processing system may include a plurality of instruction caches and front-end units each to process an individual thread from a corresponding one of the instruction caches, a pl... | 11/03/2011 |
| 20110246720 | STORAGE SYSTEM WITH MULTIPLE CONTROLLERS A first controller, and a second controller coupled to the first controller via a first path are provided. The first controller includes a first relay circuit which is a circuit that controls data transfer, and a first processor coupled to the first relay circuit via a ... | 10/06/2011 |
| 20110231612 | PRE-FETCHING FOR A SIBLING CACHE One embodiment provides a system that pre-fetches into a sibling cache. During operation, a first thread executes in a first processor core associated with a first cache, while a second thread associated with the first thread simultaneously executes in a second processo... | 09/22/2011 |
| 20110219189 | STORAGE SYSTEM AND REMOTE COPY CONTROL METHOD FOR STORAGE SYSTEM A storage system maintains consistency of the stored contents between volumes even when a plurality of remote copying operations are executed asynchronously. A plurality of primary storage control devices and a plurality of secondary storage control devices are connecte... | 09/08/2011 |
| 20110219188 | CACHE AS POINT OF COHERENCE IN MULTIPROCESSOR SYSTEM In a multiprocessor system, a conflict checking mechanism is implemented in the L2 cache memory. Different versions of speculative writes are maintained in different ways of the cache. A record of speculative writes is maintained in the cache directory. Conflict checkin... | 09/08/2011 |
| 20110213931 | NON BLOCKING REHASHING An apparatus and a method operating on data at a server node of a data grid system with distributed cache is described. A coordinator receives a request to change a topology of a cache cluster from a first group of cache nodes to a second group of cache nodes. The reque... | 09/01/2011 |
| 20110208914 | STORAGE SYSTEM AND METHOD OF OPERATING THEREOF There are provided a storage system, storage control unit and method of operating thereof. A storage system comprises a permanent storage subsystem comprising a first cache memory and a non-volatile storage medium, and a storage control unit operatively coupled to said ... | 08/25/2011 |
| 20110197013 | CACHE SYSTEM A cache system includes a primary cache memory configured to input and output data between a computation unit, the primary cache memory includes multi-port memory units each including a storing unit that stores unit data having a first data size, a writing unit that sim... | 08/11/2011 |
| 20110191541 | TECHNIQUES FOR DISTRIBUTED CACHE MANAGEMENT Techniques for distributed cache management are provided. A server having backend resource includes a global cache and a global cache agent. Individual clients each have client cache agents and client caches. When data items associated with the backend resources are add... | 08/04/2011 |
| 20110179308 | Auxiliary circuit structure in a split-lock dual processor system A multiple-processor system 2 is provided where each processor 4-0, 4-1 can be dynamically switched between running in a locked mode where one processor 4-1 checks the operation of the other processor 4-0 and a spl... | 07/21/2011 |
| 20110167223 | BUFFER MEMORY DEVICE, MEMORY SYSTEM, AND DATA READING METHOD Memory access is accelerated by performing a burst read without any problems caused due to rewriting of data. A buffer memory device reads, in response to a read request from a processor, data from a main memory including cacheable and uncacheable areas. The buffer memo... | 07/07/2011 |
| 20110153911 | METHOD AND SYSTEM FOR ACHIEVING DIE PARALLELISM THROUGH BLOCK INTERLEAVING A method and system for achieving die parallelism through block interleaving includes non-volatile memory having a multiple non-volatile memory dies, where each die has a cache storage area and a main storage area. A controller is configured to receive data and write se... | 06/23/2011 |
| 20110153941 | Multi-Autonomous System Anycast Content Delivery Network A content delivery network includes first and second sets of cache servers, a domain name server, and an anycast island controller. The first set of cache servers is hosted by a first autonomous system and the second set of cache servers is hosted by a second autonomous... | 06/23/2011 |
| 20110131376 | METHOD AND APPARATUS FOR TILE MAPPING TECHNIQUES An approach for improving tile-map caching techniques is provided. Whether a tile object is stored in a first cache that is configured to store a plurality of tile objects associated with a map is determined. It is also determined whether a resource locator associated w... | 06/02/2011 |
| 20110082981 | MULTIPROCESSING CIRCUIT WITH CACHE CIRCUITS THAT ALLOW WRITING TO NOT PREVIOUSLY LOADED CACHE LINES Data is processed using a first and second processing circuit (12) coupled to a background memory (10) via a first and second cache circuit (14, 14′) respectively. Each cache circuit (14, 14′) stores cache lines, state information definin... | 04/07/2011 |
| 20110082980 | HIGH PERFORMANCE UNALIGNED CACHE ACCESS A cache memory device and method for operating the same. One embodiment of the cache memory device includes an address decoder decoding a memory address and selecting a target cache line. A first cache array is configured to output a first cache entry associated with th... | 04/07/2011 |
| 20110072212 | CACHE MEMORY CONTROL APPARATUS AND CACHE MEMORY CONTROL METHOD A cache memory controller searches a second cache tag memory holding a cache state information indicating whether any of multi-processor cores storing a registered address of information registered within its own first cache memory exists. When a target address coincide... | 03/24/2011 |
| 20110060879 | SYSTEMS AND METHODS FOR PROCESSING MEMORY REQUESTS A processing system is provided. The processing system includes a first processing unit coupled to a first memory and a second processing unit coupled to a second memory. The second memory comprises a coherent memory and a private memory that is private to the second pr... | 03/10/2011 |
| 20110055467 | DATA AREA MANAGING METHOD IN INFORMATION RECORDING MEDIUM AND INFORMATION PROCESSOR EMPLOYING DATA AREA MANAGING METHOD Area management information is cached in a cache memory by controlling the access size when an information processor accesses the area management information in an information recording medium. When the processing content of the information processor is to retrieve a fr... | 03/03/2011 |
| 20110055610 | PROCESSOR AND CACHE CONTROL METHOD A processor and a cache control method are provided herein. The processor includes a plurality of caches and a control unit. The caches are respectively controlled by a plurality of cache enable signals to be activated. The control unit generates the cache enable signal... | 03/03/2011 |
| 20110029751 | ENHANCED BLOCK COPY The present disclosure includes methods and apparatus for an enhanced block copy. One embodiment includes reading data from a source block located in a first portion of the memory device, and programming the data to a target block located in a second portion of the memo... | 02/03/2011 |
| 20100332700 | DATA STOREWIDTH ACCELERATOR Data storage controllers and data storage devices employing lossless or lossy data compression and decompression to provide accelerated data storage and retrieval bandwidth. In one embodiment of the invention, a composite disk controller provides data storage and retrie... | 12/30/2010 |
| 20100332755 | METHOD AND APPARATUS FOR USING A SHARED RING BUFFER TO PROVIDE THREAD SYNCHRONIZATION IN A MULTI-CORE PROCESSOR SYSTEM An apparatus and method for improving synchronization between threads in a multi-core processor system are provided. An apparatus includes a memory, a first processor core, and a second processor core. The memory includes a shared ring buffer for storing data units, and... | 12/30/2010 |
| 20100332756 | PROCESSING OUT OF ORDER TRANSACTIONS FOR MIRRORED SUBSYSTEMS Methods and apparatus relating to processing out of order transactions for mirrored subsystems are described. In one embodiment, a device (that is mirroring data from another device) includes a cache to track out of order write operations prior to writing the data from ... | 12/30/2010 |
| 20100293331 | STORAGE SYSTEM AND DATA MANAGEMENT METHOD A storage system, which is coupled to a computer, includes a storage device, a controller, a plurality of cache memory units, and a connecting unit. Each of the plurality of cache memory units includes: a cache memory for storing data; an auxiliary storage device for ho... | 11/18/2010 |
| 20100293332 | CACHE ENUMERATION AND INDEXING In response to a request including a state object, which can indicate a state of an enumeration of a cache, the enumeration can be continued by using the state object to identify and send cache data. Also, an enumeration of cache units can be performed by traversing a d... | 11/18/2010 |
| 20100275053 | CLOCK SKEW MEASUREMENT FOR MULTIPROCESSOR SYSTEMS Systems and methods (“utility”) for providing more accurate clock skew measurements between multiple CPUs in a multiprocessor computer system by utilizing the cache control or management protocols of the CPUs in the multiprocessor system. The utility may utilize a t... | 10/28/2010 |
| 20100262781 | Loading Data to Vector Renamed Register From Across Multiple Cache Lines A load instruction that accesses data cache may be off natural alignment, which causes a cache line crossing to complete the access. The illustrative embodiments provide a mechanism for loading data across multiple cache lines without the need for an accumulation regist... | 10/14/2010 |
| 20100257316 | Virtual Barrier Synchronization Cache Castout Election A data processing system includes an interconnect fabric, a system memory coupled to the interconnect fabric and including a virtual barrier synchronization region allocated to storage of virtual barrier synchronization registers (VBSRs), and a plurality of processing u... | 10/07/2010 |
| 20100241808 | CACHE-LINE AWARE COLLECTION FOR RUNTIME ENVIRONMENTS Target data is allocated into caches of a shared-memory multiprocessor system during a runtime environment. The target data includes a plurality of data items that are allocated onto separate cache lines. Each data item is allocated on a separate cache line regardless o... | 09/23/2010 |
| 20100235716 | DUAL PORTED REPLICATED DATA CACHE A dual ported replicated data cache. The cache is configured for storing input data blocks. The cache includes an augmenter for producing an augmented data block with parity information from the input data block, a first memory array for storing the augmented data block... | 09/16/2010 |
| 20100211743 | INFORMATION PROCESSING APPARATUS AND METHOD OF CONTROLLING SAME Disclosed is an information processing apparatus equipped with first and second CPUs, as well as a method of controlling this apparatus. When the first CPU launches an operating system for managing a virtual memory area that includes a first cache area for a device, the... | 08/19/2010 |
| 20100211742 | CONVEYING CRITICAL DATA IN A MULTIPROCESSOR SYSTEM A system for conveying critical and non-critical words of multiple cache lines includes a first node interface of a first processing node receiving, from a first processor, a first request identifying a critical word of a first cache line and a second request identifyin... | 08/19/2010 |
| 20100180208 | SERVER SIDE DATA CACHE SYSTEM In an example embodiment, a system and method to store and retrieve application data from a cache and a database are provided. The example method may comprise receiving location data associated with application data from a user device, using the location data to determi... | 07/15/2010 |
| 20100169582 | Obtaining data for redundant multithreading (RMT) execution In one embodiment, the present invention includes a method for providing a cache block in an exclusive state to a first cache and providing the same cache block in the exclusive state to a second cache when cores accessing the two caches are executing redundant threads.... | 07/01/2010 |
| 20100169579 | READ AND WRITE MONITORING ATTRIBUTES IN TRANSACTIONAL MEMORY (TM) SYSTEMS A method and apparatus for monitoring memory accesses in hardware to support transactional execution is herein described. Attributes are monitor accesses to data items without regard for detection at physical storage structure granularity, but rather ensuring monitoring... | 07/01/2010 |
| 20100131716 | CACHE MEMORY SHARING IN A MULTI-CORE PROCESSOR (MCP) This invention describes an apparatus, computer architecture, memory structure, memory control, and cache memory operation method for multi-core processor. A logic core shares requests when faced with immediate cache memory units having low yield or deadly performance. ... | 05/27/2010 |
