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"That’s an amazing invention, but who would ever want to use one of them?"
President Rutherford B. Hayes ; Said in 1876, after Alexander Graham Bell demonstrated the telephone to him at the White House
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| Application No. | Application Title | Issue Date |
| 20120131264 | STORAGE DEVICE According to one embodiment, a storage device comprises a first storage unit having blocks, each including pages, a second storage unit having a free block list, and a free page list, and a control unit. In write data in units of blocks, the control unit generates compr... | 05/24/2012 |
| 20120131266 | MEMORY CONTROLLER, DATA STORAGE SYSTEM INCLUDING THE SAME, METHOD OF PROCESSING DATA A data storage system includes a controller configured to receive data and data information about the data from a host, analyze the data information, detect whether the data has been compressed, and compress the data according to a detection result; and a nonvolatile me... | 05/24/2012 |
| 20120131263 | MEMORY STORAGE DEVICE, MEMORY CONTROLLER THEREOF, AND METHOD FOR RESPONDING HOST COMMAND A memory storage device, a memory controller thereof, and a method for responding host commands are provided. The memory storage device has a flash memory chip and a buffer memory. The present method includes receiving a write command issued by a host system and determi... | 05/24/2012 |
| 20120131269 | ADAPTIVE MEMORY SYSTEM FOR ENHANCING THE PERFORMANCE OF AN EXTERNAL COMPUTING DEVICE An adaptive memory system is provided for improving the performance of an external computing device. The adaptive memory system includes a single controller, a first memory type (e.g., Static Random Access Memory or SRAM), a second memory type (e.g., Dynamic Random Acce... | 05/24/2012 |
| 20120131262 | Method and Apparatus for EEPROM Emulation for Preventing Data Loss in the Event of a Flash Block Failure A defect resistant EEPROM emulator (110) uses one or more redundant and/or spare blocks (213) in addition to active and alternate blocks (211, 212) and stores a duplicate copy of EEPROM data records either in the active and redundant blocks or in du... | 05/24/2012 |
| 20120131265 | WRITE CACHE STRUCTURE IN A STORAGE SYSTEM A method of writing data units to a storage device. The data units are cached in a first level cache sorted by logical address. A group (Gj) of sorted data units is transferred from the first level cache to a second level cache embodied in a solid state memor... | 05/24/2012 |
| 20120131268 | DATA STORAGE DEVICE A data storage device comprising: at least two flash devices for storing data; a circuit board, wherein each of the flash devices are integrated on the circuit board; a controller integrated on the circuit board for reading and writing to each flash devices, wherein the... | 05/24/2012 |
| 20120131267 | MEMORY DEVICE DISTRIBUTED CONTROLLER SYSTEM A memory device distributed controller circuit distributes memory control functions amongst a plurality of memory controllers. A master controller receives an interpreted command and activates the appropriate slave controllers depending on the command. The slave control... | 05/24/2012 |
| 20120131270 | STORAGE SYSTEM AND CONTROL METHOD THEREOF Proposed are a storage system and its control method capable of dealing with the unique problems that arise when using a nonvolatile memory as the memory device while effectively preventing performance deterioration. This storage system is provided with a plurality of m... | 05/24/2012 |
| 20120131261 | SUB-BLOCK ACCESSIBLE NONVOLATILE MEMORY CACHE Subject matter disclosed herein relates to sub-block accessible cache memory.... | 05/24/2012 |
| 20120110250 | MEETHOD, SYSTEM AND COMPUTER READABLE MEDIUM FOR COPY BACK Systems, computer readable media and methods for updating a flash memory device involve procedures for transferring, from a flash memory device to an external controller, only a portion of a data entity; and determining, by the external controller, based upon the portio... | 05/03/2012 |
| 20120110247 | MANAGEMENT OF CACHE MEMORY IN A FLASH CACHE ARCHITECTURE A method for managing cache memory in a flash cache architecture. The method includes providing a storage cache controller, at least a flash memory comprising a flash controller, and at least a backend storage device, and maintaining read cache metadata for tracking on ... | 05/03/2012 |
| 20120110251 | PROCESSOR-BUS-CONNECTED FLASH STORAGE MODULE A system includes multiple nodes coupled using a network of processor buses. The multiple nodes include a first processor node, including one or more processing cores and main memory, and a flash memory node coupled to the first processor node via a first processor bus ... | 05/03/2012 |
| 20120110249 | MEMORY SYSTEM, DATA STORAGE DEVICE, USER DEVICE AND DATA MANAGEMENT METHOD THEREOF A data management method of a data storage device having a data management unit different from a data management unit of a user device receives information regarding a storage area of a file to be deleted, from the user device, selects a storage area which matches with ... | 05/03/2012 |
| 20120110248 | ELECTRONIC FLASH MEMORY EXTERNAL STORAGE METHOD AND DEVICE An electronic flash memory external storage method and device for data processing system includes firmware which directly controls the access of electronic storage media and implements standard interface functions, adopts particular reading and writing formats of the ex... | 05/03/2012 |
| 20120110252 | System and Method for Providing Performance-Enhanced Rebuild of a Solid-State Drive (SSD) in a Solid-State Drive Hard Disk Drive (SSD HDD) Redundant Array of Inexpensive Disks 1 (Raid 1) Pair The present invention is a method for implementing a storage system. The storage system may include a disk array having a disk drive pair which includes a solid-state disk drive and a hard disk drive. The method may include the step of copying a data subset of a data se... | 05/03/2012 |
| 20120110243 | DATA WRITING METHOD, MEMORY CONTROLLER, AND MEMORY STORAGE APPARATUS A data writing method for a rewritable non-volatile memory module is provided, the rewritable non-volatile memory module has a plurality of physical blocks, each of the physical blocks has a plurality of physical pages, a portion of the physical blocks are mapped to a p... | 05/03/2012 |
| 20120110244 | COPYBACK OPERATIONS Methods and systems for copyback operations are described. One or more methods include reading data from a first memory unit of a memory device responsive to a copyback command, performing signal processing on the data using a signal processing component local to the me... | 05/03/2012 |
| 20120110253 | COMBINED MEMORY AND STORAGE DEVICE IN AN APPARATUS FOR DATA PROCESSING The invention concerns an apparatus for data processing comprising a central processing unit and a non volatile random access memory. The central processing unit and the non volatile random access memory are connected via a memory bus. The data related to an operating s... | 05/03/2012 |
| 20120110240 | Method and System for Memory Controller Calibration A method for calibration of a memory controller may include determining if an unused memory location exists in memory. The method may include writing a first pattern to the unused memory location in response to a determination that the unused memory location exists. The... | 05/03/2012 |
| 20120110241 | SYSTEM FOR NAND FLASH PARAMETER AUTO-DETECTION A system comprising a NAND flash memory device having a multiplicity of parameters; a flash controller configured to perform a NAND flash memory parameter automatic detection process including reading a device identifier of the NAND flash memory device and proceeding if... | 05/03/2012 |
| 20120110242 | PROGRAMMABLE MEMORY CONTROLLER A memory controller, in one embodiment, includes a command translation data structure, a front end and a back end. The command translation data structure maps command operations to primitives, wherein the primitives are decomposed from command operations determined for ... | 05/03/2012 |
| 20120110376 | Systems and Methods for Managing End of Life in a Solid State Drive Various embodiments of the present invention provide systems and methods for managing solid state drives. As an example, a storage system is described that include at least a first flash memory block and a second flash memory block, and a control circuit. The first flas... | 05/03/2012 |
| 20120110239 | Causing Related Data to be Written Together to Non-Volatile, Solid State Memory A first write request that is associated with a first logical address is received via a collection of write requests targeted to a non-volatile, solid state memory. It is determined whether the logical address is related to logical addresses of one or more other write r... | 05/03/2012 |
| 20120110245 | Data writing method and writing device for an electronic erasable read only dynamic memory A data writing method for an EEPROM in an electronic device is performed by a writing device. The electronic device includes a system unit generating a system voltage and a write-protection voltage. The writing device includes a processor stored with data to be written,... | 05/03/2012 |
| 20120110246 | EXECUTE-IN-PLACE MODE CONFIGURATION FOR SERIAL NON-VOLATILE MEMORY Example embodiments for configuring a serial non-volatile memory device for an execute-in-place mode may comprise a non-volatile configuration register to store an execute-in-place mode value that may be read at least in part in response to power being applied to the me... | 05/03/2012 |
| 20120084493 | NON-VOLATILE MEMORY DEVICE HAVING ASSIGNABLE NETWORK IDENTIFICATION Memory devices and methods disclosed such as a memory device having a plurality of memory dies where each die includes a network identification that uniquely identifies the memory die on a bus. Access for each memory die to the bus can be scheduled by a bus controller.... | 04/05/2012 |
| 20120084494 | MEMORY FOR ACCESSING MULTIPLE SECTORS OF INFORMATION SUBSTANTIALLY CONCURRENTLY A memory storage system of an embodiment includes a non-volatile memory unit and memory control circuitry coupled to the memory unit. The memory control circuitry is configured to access multiple sectors of information substantially concurrently.... | 04/05/2012 |
| 20120084495 | SEMICONDUCTOR PROGRAMMABLE DEVICE An ePLX unit includes a logic unit having an SRAM and a MUX, and a switch unit having an SRAM and a TG for establishing wiring connection in the logic unit. When a composite module is set in the first mode, an Add/Flag control unit uses the SRAMs as a data field and a f... | 04/05/2012 |
| 20120084489 | SYNCHRONIZED MAINTENANCE OPERATIONS IN A MULTI-BANK STORAGE SYSTEM A method and system for managing maintenance operations in a multi-bank non-volatile storage device is disclosed. The method includes receiving a data write command and associated data from a host system for storage in the non-volatile storage device and directing a hea... | 04/05/2012 |
| 20120084490 | METHOD FOR CHANGING READ PARAMETER FOR IMPROVING READ PERFORMANCE AND APPARATUSES USING THE SAME A memory system including a non-volatile memory device and a memory controller is provided. When a read operation on a first data initially output from the non-volatile memory device during a first read operation is successful, the memory controller may change a read vo... | 04/05/2012 |
| 20120084491 | Flash Memory for Code and Data Storage A flash memory for code and data storage includes a code memory array having fast read access and suitability for execute in place, a data memory array having the characteristics of low bit cost and high density storage, and a suitable interface to provide access to bot... | 04/05/2012 |
| 20120084492 | STORAGE SYSTEM LOGICAL BLOCK ADDRESS DE-ALLOCATION MANAGEMENT AND DATA HARDENING Storage system Logical Block Address (LBA) de-allocation management and data hardening provide improvements in performance, efficiency, and utility of use. Optionally, LBA de-allocation information in a first format (e.g. associated with a first protocol) is converted t... | 04/05/2012 |
| 20120072651 | MEMORY CONTROLLER INTERFACE A memory controller interface, mobile device and method are provided. The memory controller interface can allow a processor designed and configured to operate with NOR flash and static random access memory SRAM devices to instead operate using NAND flash and synchronous... | 03/22/2012 |
| 20120072647 | Different types of memory integrated in one chip by using a novel protocol A semiconductor chip contains four different memory types, EEPROM, NAND Flash, NOR Flash and SRAM, and a plurality of major serial/parallel interfaces such as I2C, SPI, SDI and SQI in one memory chip. The memory chip features write-while-write and read-while-... | 03/22/2012 |
| 20120072639 | Selection of Units for Garbage Collection in Flash Memory A data structure is formed that references a garbage collection metric for each of a plurality of associated garbage collection units of a flash memory device. Each garbage collection metric is based on one or more device state characteristics of the associated garbage ... | 03/22/2012 |
| 20120072648 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE A nonvolatile semiconductor memory device in accordance with an embodiment includes: a memory cell array having electrically rewritable nonvolatile memory cells; and a control unit. The control unit performs control of repeating a write operation, a write verify operati... | 03/22/2012 |
| 20120072652 | MULTI-LEVEL BUFFER POOL EXTENSIONS A buffer manager that manages blocks of memory amongst multiple levels of buffer pools. For instance, there may be a first level buffer pool for blocks in first level memory, and a second level buffer pool for blocks in second level memory. The first level buffer pool e... | 03/22/2012 |
| 20120072653 | MEMORY DEVICE WITH USER CONFIGURABLE DENSITY/PERFORMANCE The memory device is comprised of a memory array having a plurality of memory cells that are organized into memory blocks. Each memory cell is capable of storing a selectable quantity of data bits (e.g., multiple level cells or a single bit per cell). Control circuitry ... | 03/22/2012 |
| 20120072646 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF CONTROLLING MEMORY According to one embodiment, a semiconductor integrated circuit device includes a non-volatile memory, a storing module, and a processing module. The non-volatile memory is having a first area and a second area. The storing module is configured to store a second program... | 03/22/2012 |
