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| Application No. | Application Title | Issue Date |
| 20120047310 | Crossbar circuitry for applying a pre-selection prior to arbitration between transmission requests and method of operation of such crossbar circuitry Crossbar circuitry has data input and output paths, and at each intersection between a data input and output path, a crossbar cell is provided. A transmission circuit is responsive to a stored routing value to couple a data input path to a selected data output path. Pre... | 02/23/2012 |
| 20110320678 | CROSSPOINT SWITCH FOR USE IN VIDEO AND OTHER APPLICATIONS A crosspoint selector switch for simultaneously supporting multiple data formats having different switch reconfiguration timing requirements, comprising; a configurable switch section for selectively connecting outputs thereof to receive data from respective inputs ther... | 12/29/2011 |
| 20110283038 | Information processing system, information processing device, control method for information processing device, and computer-readable recording medium An information processing system including plural information processing devices multi-dimensionally connected with one another, where each of the information processing devices includes first and second receiving storage devices to store data allocated to first and sec... | 11/17/2011 |
| 20110258361 | PETAFLOPS ROUTER Disclosed is a method and system for performing operations on at least one input data vector in order to produce at least one output vector to permit easy, scalable and fast programming of a petascale equivalent supercomputer. A PetaFlops Router may comprise one or more... | 10/20/2011 |
| 20110185101 | SCALABLE DISTRIBUTED MEMORY AND I/O MULTIPROCESSOR SYSTEM A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises a... | 07/28/2011 |
| 20110173358 | EAGER PROTOCOL ON A CACHE PIPELINE DATAFLOW A master device sends a request to communicate with a slave device to a switch. The master device waits for a period of cycles the switch takes to decide whether the master device can communicate with the slave device, and the master device sends data associated with th... | 07/14/2011 |
| 20110138098 | Crossbar circuitry for applying an adaptive priority scheme and method of operation of such crossbar circuitry Crossbar circuitry has an array of data input and output paths where the data output paths are transverse to the data input paths. At each intersection between a data input path and a data output path, a crossbar cell is provided which includes a configuration storage c... | 06/09/2011 |
| 20110138099 | Method for communicating between nodes and server apparatus According to an aspect of the embodiment, an input/output device transmits a message to a first node controller of a parent node which is set in advance via a cross bar. At this point, the cross bar generates information based on node information of the input/output dev... | 06/09/2011 |
| 20110082961 | Sharing Data Crossbar for Reads and Writes in a Data Cache The invention sets forth an L1 cache architecture that includes a crossbar unit configured to transmit data associated with both read data requests and write data requests. Data associated with read data requests is retrieved from a cache memory and transmitted to the c... | 04/07/2011 |
| 20110072177 | VIRTUAL CHANNELS FOR EFFECTIVE PACKET TRANSFER The invention sets forth a crossbar unit that includes multiple virtual channels, each virtual channel being a logical flow of data within the crossbar unit. Arbitration logic coupled to source client subsystems is configured to select a virtual channel for transmitting... | 03/24/2011 |
| 20110060860 | BACKPLANE NETWORK DISTRIBUTION A backplane arrangement 200; 500 and method for distributing network connections in said backplane arrangement 200; 500 comprising a number of board positions Ac-Fc; Gc-Kc each arranged to operatively receive a board Ab-Fb; Gb-Kb, and a backplane-network a... | 03/10/2011 |
| 20110060862 | Systems and Methods for Switchable Memory Configuration Various embodiments of the disclosure provide systems, methods and circuits for implementation and use of a memory system. As one example, a memory system is disclosed that includes a plurality of memory devices and a configuration circuit. The configuration circuit inc... | 03/10/2011 |
| 20110055452 | METHOD AND PROGRAM FOR MEMORY RELOCATION CONTROL OF COMPUTER, AND COMPUTER SYSTEM A computer system comprises a computer that includes a plurality of CPU sockets including one or more CPU cores, a crossbar switch, and a memory controller each, and memories connected under the respective plurality of CPU sockets, the plurality of CPU sockets being con... | 03/03/2011 |
| 20110035529 | Partitioning a Crossbar Interconnect in a Multi-Channel Memory System A method includes identifying a first set of masters and a second set of masters from a plurality of masters. The plurality of masters have access to a multi-channel memory via a crossbar interconnect. The method includes partitioning the crossbar interconnect into a pl... | 02/10/2011 |
| 20110035530 | Network system, information processing apparatus, and control method for network system A network system includes a crossbar switch, and a plurality of crossbar interfaces having ports connected to the crossbar switch. A bypass route directly connects crossbar interfaces forming a group in which a frequency of use of the ports is greater than or equal to a... | 02/10/2011 |
| 20110016259 | Information processing device, data transfer circuit, and control method of information processing device Cross bar control circuits are connected to each other by two buses, which are a broadcast bus for transmitting a broadcast packet from a system board to all system boards other than the system board and a point-to-point bus for transmitting a unicast packet from a syst... | 01/20/2011 |
| 20100274957 | SYSTEM AND APPARATUS WITH A MEMORY CONTROLLER CONFIGURED TO CONTROL ACCESS TO RANDOMLY ACCESSIBLE NON-VOLATILE MEMORY An apparatus includes a printed circuit board with a plurality of printed circuit board traces, a memory controller mounted on the printed circuit board coupled to one or more of the plurality of printed circuit board traces, a plurality of non-volatile type of memory i... | 10/28/2010 |
| 20100274946 | INTEGRATED CIRCUIT AND INFORMATION PROCESSING DEVICE In an LSI system using an on-chip bus, when a transfer on the bus is delayed due to a fully loaded buffer in a destination module, a source module cannot proceed to the next processing. Such an unwanted situation is eliminated by plural transferring buffers which are pr... | 10/28/2010 |
| 20100229050 | APPARATUS HAVING FIRST BUS AND SECOND BUS CONNECTABLE TO I/O DEVICE, INFORMATION PROCESSING APPARATUS AND METHOD OF CONTROLLING APPARATUS An apparatus connected to a first and second buses, the apparatus having a first controller that transforms first form data into second form data, transforms second form data into first form data, and outputs the transformed data, a second controller that transforms fir... | 09/09/2010 |
| 20100211720 | Crossbar circuitry and method of operation of such crossbar circuitry Crossbar circuitry, and a method of operation of such crossbar circuitry, are provided. The crossbar circuitry has an array of data input paths and data output paths where the data output paths are transverse to the data input paths. At each intersection between a data ... | 08/19/2010 |
| 20100211718 | METHOD AND APPARATUS FOR CONGESTION-AWARE ROUTING IN A COMPUTER INTERCONNECTION NETWORK The present disclosure relates to an example of a method for a first router to adaptively determine status within a network. The network may include the first router, a second router and a third router. The method for the first router may comprise determining status inf... | 08/19/2010 |
| 20100211719 | Crossbar circuitry and method of operation of such crossbar circuitry Crossbar circuitry, and a method of operation of such crossbar circuitry, are provided. The crossbar circuitry has an array of data input paths and data output paths where the data output paths are transverse to the data input paths. At each intersection between a data ... | 08/19/2010 |
| 20100138586 | ADAPTIVE AND MODULAR UPS SYSTEM AND METHOD An uninterruptible power supply (UPS) system that may incorporate a battery subsystem including at least one battery for generating electrical power, and a UPS subsystem including at least one power module. At least one first bus system may couple the battery subsystem ... | 06/03/2010 |
| 20100077127 | Flexible Connection Scheme Between Multiple Masters and Slaves The present invention describes a flexible routing scheme between masters and slaves in complex digital systems. The routing scheme is optimized for maximum versatility and configurability using switched resources in the form of configurable crossbar switches.... | 03/25/2010 |
| 20100005213 | Access Table Lookup for Bus Bridge Cross-bar segment routing and access table address remapping functions are combined within a cross-bar of a system-on-a-chip. In this manner, address remapping may occur prior to segment routing. One or more access table caching registers may be included for each master... | 01/07/2010 |
| 20090319717 | SCALABLE DISTRIBUTED MEMORY AND I/O MULTIPROCESSOR SYSTEMS AND ASSOCIATED METHODS A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises a... | 12/24/2009 |
| 20090282182 | MULTIPLE PROCESSOR SYSTEM AND METHOD INCLUDING MULTIPLE MEMORY HUB MODULES A processor-based electronic system includes several memory modules arranged in first and second ranks. The memory modules in the first rank are directly accessed by any of several processors, and the memory modules in the second rank are accessed by the processors thro... | 11/12/2009 |
| 20090248948 | System and Method for A Distributed Crossbar Network Using a Plurality of Crossbars A system and method for single hop, processor-to-processor communication in a multiprocessing system over a plurality of crossbars are disclosed. Briefly described, one embodiment is a multiprocessing system comprising a plurality of processors having a plurality of hig... | 10/01/2009 |
| 20090249127 | METHOD AND SYSTEM FOR STORING DATA FROM A PLURALITY OF PROCESSORS A method of storing data from a plurality of processors comprising the steps of (a) transferring data along a first bus (b) connectable between a first processor and a synchronising means and operable with a first protocol; (c) synchronising the synchronising means with... | 10/01/2009 |
| 20090240866 | Multi-port memory and computer system provided with the same A multi-port memory, comprising: m (m≧2) input/output ports independent of one another; n (n≧2) memory banks independent of one another; and a route switching circuit capable of optionally setting signal routes of a command, an address, and input/output data between... | 09/24/2009 |
| 20090210610 | Computer system, data relay device and control method for computer system A computer system includes a plurality of system boards each of which includes two systems arranged in a duplicated structure and a data relay device. The data relay device includes a degeneration determining unit that determines whether each of the systems is degenerat... | 08/20/2009 |
| 20090198864 | NETWORK SWITCH AND METHOD OF SWITCHING IN NETWORK A network switch with a plurality of crossbar switches that is available to suppress increase in the circuit scale is provided. The network switch has: the plurality of crossbar switches that transfer unit data in a specified format; a receiving side transfer unit that ... | 08/06/2009 |
| 20090193172 | CROSS-BAR SWITCHING IN AN EMULATION ENVIRONMENT A system and method are disclosed for crossbar switching in an emulation environment. The switch is designed to coordinate scheduling between different crossbars in the system and to be dynamically reconfigurable during operation. In one aspect, a crossbar switch includ... | 07/30/2009 |
| 20090177870 | Method and System for a Wiring-Efficient Permute Unit A method of providing wiring efficiency in a permute unit. Multiple selectors receive input data and shared control signals from multiple register files. The permute unit includes multiple multiplexors (MUXs) coupled to multiple logical AND gates. The multiple logical A... | 07/09/2009 |
| 20090172242 | SYSTEM AND METHOD FOR CONNECTING A MASTER DEVICE WITH MULTIPLE GROUPINGS OF SLAVE DEVICES VIA A LINBUS NETWORK A LINBUS communication network comprises a microcontroller unit containing processing circuitry for performing predefined digital processing functions. LINBUS communication network hardware is located within the microcontroller unit for digitally communicating with an o... | 07/02/2009 |
| 20090144480 | MULTI-PROCESSOR SYSTEM ON CHIP PLATFORM AND DVB-T BASEBAND RECEIVER USING THE SAME A multi-processor system on chip (SoC) platform and a DVB-T baseband receiver using the same are disclosed. The multi-processor SoC platform includes a first processor, at least one second processor, at least one slave device communicating with the first processor and t... | 06/04/2009 |
| 20090089478 | Crossbar channel router having a distributed arbitration scheme A router is provided that includes a plurality of lanes to receive inbound data from a plurality of different input ports. The router may further include a shared crossbar channel coupled to each of the lanes and to a plurality of output ports, the crossbar channel to r... | 04/02/2009 |
| 20090063702 | CROSSBAR APPARATUS FOR A FORWARDING TABLE MEMORY IN A ROUTER A router including a lookup execution unit including a plurality of stages, a forwarding table memory arranged in hierarchy including addressable sectors, blocks, and entries, and a crossbar having an address crossbar for selectively coupling one of the plurality of sta... | 03/05/2009 |
| 20090037639 | JTAGCHAIN Bus Switching and Configuring Device A JTAG bus cross point switching device that is commanded by the same bus which it configures. In a preferred embodiment a JTAG chain includes a cross point switching device that is capable of adding, omitting, or rearranging devices on a JTAG bus. The switching device ... | 02/05/2009 |
| 20080307150 | Optimized Switching Method There is disclosed a bus optimization technique. Pursuant to the bus optimization technique, the output buffer and output logic are removed from port units of a switch and are included with a control matrix in the switch. Data units received in a first port unit of a pl... | 12/11/2008 |
