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| Application No. | Application Title | Issue Date |
| 20120054404 | METHODS AND APPARATUS FOR IMPROVED HOST/INITIATOR UTILIZATION IN SERIAL ADVANCED TECHNOLOGY ATTACHMENT COMMUNICATION Methods and apparatus for improved performance in communications between a SAS/STP initiator device and a plurality of SATA storage devices coupled with the initiator through an enhanced switching device. The switching device is enhanced in accordance with features and ... | 03/01/2012 |
| 20110296073 | TIME ALIGNING CIRCUIT AND TIME ALIGNING METHOD FOR ALIGNING DATA TRANSMISSION TIMING OF A PLURALITY OF LANES A time aligning circuit includes a plurality of buffers, a plurality of delay selectors, a plurality of adjustment symbol generators, and a controller. Each buffer receives an ordered set on a corresponding lane. Each delay selector delays an output of the ordered set o... | 12/01/2011 |
| 20110296158 | HAND-HELD TEST METER WITH DISRUPTION AVOIDANCE CIRCUITRY A hand-held test meter for use with an analytical test strip configured for the determination of an analyte in a bodily fluid sample includes a USB interface, a microcontroller block configured for boot strap loading (BSL) of data into the hand-held test meter via a ser... | 12/01/2011 |
| 20110289253 | INTERCONNECTION METHOD AND DEVICE, FOR EXAMPLE FOR SYSTEMS-ON-CHIP Transactions of the request/response type between a first circuit module and a second circuit module operating with incompatible protocols or interfaces envisage organizing a queue of memory locations for storing transaction information items and transaction identifiers... | 11/24/2011 |
| 20110093640 | Universal Serial Bus Host Controller and Control Method Thereof A USB host controller is provided. The USB host controller is capable of communicating with multiple USB apparatuses having endpoints and sends a request to a first endpoint. The USB host controller includes a first storage and a first control unit. The first control un... | 04/21/2011 |
| 20110093639 | Secure Communications Between and Verification of Authorized CAN Devices Encrypted encoding and decoding of identification data of CAN bus devices for communications therebetween provides deterrence of theft and unauthorized access of these secure CAN bus devices. Each one of the CAN bus devices is considered a “node” on the CAN bus for ... | 04/21/2011 |
| 20110087820 | QUEUE SHARING AND RECONFIGURATION IN PCI EXPRESS LINKS In one embodiment an electronic device comprises at least one processor, at least one PCI express link, a virtual channel/sub-link flow control module, and a memory module communicatively connected to the one or more processors and comprising logic instructions which, w... | 04/14/2011 |
| 20110016251 | MULTI-PROCESSOR SYSTEM AND DYNAMIC POWER SAVING METHOD THEREOF A multi-processor system and a dynamic power saving method thereof are provided. The multi-processor system includes a plurality of processors and a chipset. Each of the processors has a plurality of standard bus request pins and a specific bus request pin, and the stan... | 01/20/2011 |
| 20100332715 | VEHICLE SYSTEM MONITORING AND COMMUNICATIONS ARCHITECTURE Systems, methods and devices are provided that allow more efficient transfer and processing of sensor information in a hierarchical data system. The system provides for a plurality of component area managers (CAM), each of the CAMS being in operable communication with a... | 12/30/2010 |
| 20100312941 | NETWORK INTERFACE DEVICE WITH FLOW-ORIENTED BUS INTERFACE A network interface device includes a bus interface that communicates over a bus with a host processor and memory, and a network interface that sends and receive data packets carrying data over a packet network. A protocol processor conveys the data between the network ... | 12/09/2010 |
| 20100306417 | Transfer of Commands And Storage Data To A Data Storage Device A controller controls transfer of commands and storage data over a databus to a data storage device. The controller comprises a memory arranged to store a queue of commands prior to the commands being transferred over the databus. The controller identifies data access c... | 12/02/2010 |
| 20100306441 | DATA TRANSFER APPARATUS AND DATA TRANSFER METHOD A data transfer apparatus for transferring data between a system bus and a local bus at a high speed is provided. A bus bridge 101 is connected between a system bus 132 and a local bus 137. Data transferred between a CPU 133, an I/O device 12/02/2010 | |
| 20100306440 | SYSTEM AND METHOD FOR SERIAL INTERFACE TOPOLOGIES A system and method for serial interface topologies is disclosed. A serial interface topology includes a replication device configured to receive control information from a controller interface. The replication device is configured to transmit two or more copies of subs... | 12/02/2010 |
| 20100299461 | INFORMATION PROCESSING APPARATUS AND IMAGE FORMING APPARATUS An information processing apparatus includes a processing unit and a control unit connected with the processing unit through a transmission line. The processing unit has multiple devices including a predetermined low-speed device. The control unit has a processing circu... | 11/25/2010 |
| 20100211714 | METHOD, SYSTEM, AND APPARATUS FOR TRANSFERRING DATA BETWEEN SYSTEM MEMORY AND INPUT/OUTPUT BUSSES Transferring data between system memory and input/output busses involves determining, via a request buffer, a memory-mapped, input/output (I/O) read request targeted for a first-in-first-out (FIFO) I/O device. The read request is targeted to a request address in a prefe... | 08/19/2010 |
| 20100191865 | COMPUTER SYSTEM AND NETWORK INTERFACESUPPORTING CLASS OF SERVICE QUEUES A data processing system adapted for high-speed network communications, a method for managing a network interface and a network interface for such system, are provided, in which processing of packets received over the network is achieved by embedded logic at the network... | 07/29/2010 |
| 20100185808 | METHODS AND SYSTEMS FOR STORING AND ACCESSING DATA IN UAS BASED FLASH-MEMORY DEVICE Methods and systems for storing and accessing data in UAS based flash memory device are disclosed. UAS based flash memory device comprises a controller and a plurality of non-volatile memories (e.g., flash memory) it controls. Controller is configured for connecting to ... | 07/22/2010 |
| 20100153611 | SYSTEM AND METHOD FOR HIGH PERFORMANCE SYNCHRONOUS DRAM MEMORY CONTROLLER The disclosed system and method enhances performance of pipelined data transactions involving FIFO buffers by implementing a transaction length indicator in a transaction header. The length indicator in the header is formed by components coupled to a memory controller t... | 06/17/2010 |
| 20100131692 | BUS BRIDGE APPARATUS AND BUS BRIDGE SYSTEM A bus bridge is connected between a general-purpose first bus and a second bus on which an interruption signal is transmitted using a packet. The bus bridge includes a plurality of reception buffers and a control section. The control section controllably switches the or... | 05/27/2010 |
| 20100115172 | BRIDGE DEVICE HAVING A VIRTUAL PAGE BUFFER A composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices. The bridge device has a virtual page buffer corresponding to each discrete memory device for storing read data from the discrete memory device, o... | 05/06/2010 |
| 20100082872 | METHOD AND APPARATUS TO OBTAIN CODE DATA FOR USB DEVICE A method and apparatus are provided that include creating an image of a page descriptor at a universal serial bus (USB) device, transferring the image of the page descriptor to a main memory, modifying a schedule list in a main memory based on the transferred image, ide... | 04/01/2010 |
| 20100077125 | SEMICONDUCTOR MEMORY DEVICE Disclosed is a semiconductor memory device includes a selector for selectively loading read inversion information and write inversion information on an inversion bus, the inversion bus for transferring the inversion information loaded by the selector, a plurality of rea... | 03/25/2010 |
| 20100070672 | METHOD AND SYSTEM FOR PROCESSING WIRELESS DIGITAL MULTIMEDIA Multimedia from a source can be wirelessly transmitted in a 60 GHz system to a display. To support rapid reads of encryption, EDID, and other data written into a slave at the display by a master at the source in accordance with I2C protocol, a master simulato... | 03/18/2010 |
| 20100011145 | Dynamic Storage Resources A storage server in a distributed content storage and access system provides a mechanism for dynamically establishing storage resources, such as buffers, with specified semantic models. For example, the semantic models support distributed control of single buffering and... | 01/14/2010 |
| 20100011137 | Method and apparatus for universal serial bus (USB) command queuing A method and apparatus for improving performance of mass storage class devices accessible via a Universal Serial Bus (USB) is presented. Performance is improved by providing support in a USB host to allow command queuing and First-Party DMA (FPDMA) to be supported in th... | 01/14/2010 |
| 20100005214 | ENHANCING BUS EFFICIENCY IN A MEMORY SYSTEM A communication interface device, system, method, and design structure for enhancing bus efficiency and utilization in a memory system. The communication interface device includes a first bus interface to communicate on a high-speed bus, a second bus interface to commun... | 01/07/2010 |
| 20090292844 | Multiprocessor gateway A multiprocessor gateway for multiple serial buses includes: multiple communication modules that are each provided for connection of one serial bus; multiple processors for processing data that are transferred in word-based fashion, via an internal system bus appurtenan... | 11/26/2009 |
| 20090276558 | LANE MERGING A buffer is associated with each of a plurality of data lanes of a multi-lane serial data bus. Data words are timed through the buffers of active ones of the data lanes. Words timed through buffers of active data lanes are merged onto a parallel bus such that data words... | 11/05/2009 |
| 20090248942 | Posted Memory Write Verification A method for verifying the proper communication of data packets from an initiator device on a PCIe data bus to a target device on the data bus. A target-specific counter on the initiator is synchronized to an initiator-specific counter on the target with the same value.... | 10/01/2009 |
| 20090235008 | PCI express multi-root IOV endpoint retry buffer controller The link layer of the multi-root PCI (peripheral component interconnect) express device stores transaction layer packets (TLPs) sent from a transaction layer in a dedicated retry buffer dedicated to the virtual hierarchy (VH) associated with the TLP. The link layer of t... | 09/17/2009 |
| 20090177831 | ROUTE AWARE SERIAL ADVANCED TECHNOLOGY ATTACHMENT (SATA ) SWITCH An embodiment of the present invention is disclosed to include a SATA Switch allowing for access by two hosts to a single port SATA device Further disclosed are embodiments for reducing the delay and complexity of the SATA Switch.... | 07/09/2009 |
| 20090172239 | Method and Device for Coupling at Least Two Independent Bus Systems There is described a method for coupling at least two independent bus systems and to a suitable device for carrying out said method, a cycle time TA, TB being assigned to each bus system and each data item from a sequence of data being transmitted ... | 07/02/2009 |
| 20090119439 | STRUCTURE COMPATIBLE WITH I2C BUS AND SYSTEM MANAGEMENT BUS AND TIMING BUFFERING APPARATUS THEREOF A structure compatible with I2C bus and system management (SM) bus is provided. The structure includes a first device having an I2C bus interface, a second device having a SM bus interface, and a timing buffering apparatus connected between the I2C bus interface and the... | 05/07/2009 |
| 20090089477 | DEADLOCK AVOIDANCE IN A BUS FABRIC Circuits, apparatus, and methods for avoiding deadlock conditions in a bus fabric. One exemplary embodiment provides an address decoder for determining whether a received posted request is a peer-to-peer request. If it is, the posted request is sent as a non-posted requ... | 04/02/2009 |
| 20090043940 | Reconstructing Transaction Order Using Clump Tags A method and system for enforcing ordering rules for transactions are presented. The method and system generates transaction clump tags for each transaction before the transactions are stored in various type specific transaction queues. A transaction clump tag decoding ... | 02/12/2009 |
| 20090037619 | DATA FLUSH METHODS A bridge capable of preventing data inconsistency is provided, in which a first master device outputs a flush request, a buffering unit buffers data or instructions, and a flush request control circuit records a buffer write pointer of the buffer according to the flush ... | 02/05/2009 |
| 20090037636 | DATA FLUSH METHODS A bridge capable of preventing data inconsistency without degrading system performance is provided, in which a buffering unit comprises a plurality of buffers, a first master device outputs a flush request to flush the buffering unit, and a flush request control circuit... | 02/05/2009 |
| 20090006705 | Hub for Supporting High Capacity Memory Subsystem A high-capacity memory subsystem architecture utilizes multiple memory modules arranged in one or more clusters, each attached to a respective hub which in turn is attached to a memory controller. Within a cluster, data is interleaved so that each data access command ac... | 01/01/2009 |
| 20080307147 | COMPUTER SYSTEM BUS BRIDGE A bus bridge between a high speed computer processor bus and a high speed output bus. The preferred embodiment is a bus bridge between a GPUL bus for a GPUL PowerPC microprocessor from International Business Machines Corporation (IBM) and an output high speed interface ... | 12/11/2008 |
| 20080307146 | STRUCTURE FOR DYNAMICALLY SCALABLE QUEUES FOR PERFORMANCE DRIVEN PCI EXPRESS MEMORY TRAFFIC A method, computer system, and PCI Express device/protocol for a design structure that enables high performance IO data transfers for multiple, different IO configurations, which include variable packet sizes and/or variable/different numbers of transactions on the IO l... | 12/11/2008 |
