Famous Patents
The first match was accidentally discovered in 1826 when John Walker scraped a stick with chemicals on the end against a stone floor.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Application No. | Application Title | Issue Date |
| 20110276739 | INTEGRATED MEMORY CONTROL APPARATUS An integrated memory control apparatus including a first interface decoder, a second interface decoder and an interface controller is provided. Wherein, the first interface decoder is coupled to a control chip through a first serial peripheral interface (SPI), the secon... | 11/10/2011 |
| 20110185102 | BUS BRIDGE AND METHOD FOR INTERFACING OUT-OF-ORDER BUS AND MULTIPLE ORDERED BUSES A method for interfacing an out-of-order bus and multiple ordered buses and a bus bridge. The bus bridge includes multiple ordered bus interfaces, where each ordered bus interface is coupled to an ordered bus. A flow control logic circuit is coupled to the out-of-order ... | 07/28/2011 |
| 20110179212 | Bus arbitration for sideband signals Systems and methods of bus arbitration for sideband signals in a multichip system are disclosed. An exemplary method comprises packaging at least one sideband signal as a micropacket. The method also comprises holding the micropacket in an outgoing sideband register. Th... | 07/21/2011 |
| 20110082961 | Sharing Data Crossbar for Reads and Writes in a Data Cache The invention sets forth an L1 cache architecture that includes a crossbar unit configured to transmit data associated with both read data requests and write data requests. Data associated with read data requests is retrieved from a cache memory and transmitted to the c... | 04/07/2011 |
| 20100321394 | INFORMATION PROCESSING DEVICE, IMAGE DISPLAY DEVICE, AND INFORMATION PROCESSING METHOD An information processing device includes: a first processing unit which asserts a first chip select signal or a second chip select signal in accordance with an address space to access; and a second processing unit accessible by the first processing unit by a first acce... | 12/23/2010 |
| 20100306439 | DATA CHECK CIRCUIT A data check circuit comprising: a request signal output circuit configured to output a request signal for requesting occupation of a bus to an arbitration circuit configured to arbitrate the occupation of the bus, when a CPU connected, as a bus master, with the bus for... | 12/02/2010 |
| 20100211720 | Crossbar circuitry and method of operation of such crossbar circuitry Crossbar circuitry, and a method of operation of such crossbar circuitry, are provided. The crossbar circuitry has an array of data input paths and data output paths where the data output paths are transverse to the data input paths. At each intersection between a data ... | 08/19/2010 |
| 20100115171 | MULTI-CHIP PROCESSOR Provided is a multiprocessor configured by stacking a plurality of unit chips each having, at least, a processor core and a memory, and the unit chip has a configuration including: a plurality of processor cores; a plurality of memories; a construction controlling unit ... | 05/06/2010 |
| 20100005213 | Access Table Lookup for Bus Bridge Cross-bar segment routing and access table address remapping functions are combined within a cross-bar of a system-on-a-chip. In this manner, address remapping may occur prior to segment routing. One or more access table caching registers may be included for each master... | 01/07/2010 |
| 20090327569 | CONTROLLED FREQUENCY CORE PROCESSOR AND METHOD FOR STARTING-UP SAID CORE PROCESSOR IN A PROGRAMMED MANNER Embodiments of the invention relate to a driven-frequency processor core. It comprises at least one processor, a non-volatile memory comprising a startup program, a bridge interconnecting buses linking the various components of said processor core, an interface componen... | 12/31/2009 |
| 20090300257 | System and Method of Increasing Data Processing on a Diagnostic Tool A method of processing J1850 requests using a scan tool having multiple processor systems is provided. The scan tool includes a first processor that processes data according to scan tool functions to assist with diagnosing and repairing a vehicle. A second processor rec... | 12/03/2009 |
| 20090216933 | METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR PIPELINE ARBITRATION A method for pipeline arbitration including receiving a first request for a shared chip interface from a first pipeline, determining whether a response bus of the shared chip interface is needed by the first request, and if it is determined that the response bus is not ... | 08/27/2009 |
| 20090164692 | DATA TRANSFER APPARATUS WITH CONTROL OF BUSES TO OPTIMIZE DATA TRANSFER A bus bridge is connected to a primary bus and a secondary bus, and relays data between a master and a target which are each connected to a different one of the primary and secondary buses. The bus bridge includes a primary bus interface, a secondary bus interface, a da... | 06/25/2009 |
| 20090164691 | IO PROCESSOR An IO processor includes an embedded central processing unit (CPU), a switch connected to the embedded CPU, an external CPU bus controller connected to the switch for optionally connecting to an external CPU, a first memory controller connected to the switch for connect... | 06/25/2009 |
| 20090106474 | Multi-Host USB Device A USB device may be simultaneously configured and accessed by two or more USB hosts. The USB device may include separate upstream ports and buffers for each host, and a multi-host capable device controller configured to respond to simultaneous USB requests received from... | 04/23/2009 |
| 20090070513 | Method and Apparatus for Distributed Direct Memory Access for Systems on Chip A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct memory access. The functional modules interface to a systems bus over whi... | 03/12/2009 |
| 20090037635 | BUS ARBITRATION DEVICE A bus arbitration device includes a top arbiter, and the hierarchical bus arbitration device also includes a first arbiter. The said first arbiter arbitrates the first kind of requests, wherein the first kind of requests relates to the first kind of master units. The sa... | 02/05/2009 |
| 20080320181 | Hardware-Based Virtualization of BIOS, Disks, Network-Interfaces, & Consoles Using a Direct Interconnect Fabric A multi-computer system has many processors that share peripherals. The peripherals are virtualized by hardware without software drivers. Remote peripherals appear to the operating system to be located on the local processor's own peripheral bus. A processor, DRAM, and ... | 12/25/2008 |
| 20080244146 | AGGREGATION OF ERROR MESSAGING IN MULTIFUNCTION PCI EXPRESS DEVICES A method of aggregating events in a PCIe (Peripheral Component Interconnect Express) multifunction device minimizes reported error messages, where several functions share a common PCIe interface logic. A predetermined number of function entities with logical gates, conn... | 10/02/2008 |
| 20080235428 | METHOD AND SYSTEM FOR DYNAMIC SWITCHING BETWEEN MULTIPLEXED INTERFACES A bridge is disclosed. The bridge comprises a first interface having at least one multiplexed clock signal line. The multiplexed clock signal line outputs first and second control signals for respectively controlling the access to first and second devices coupled to the... | 09/25/2008 |
| 20080162771 | BUS ARBITRATION SYSTEM A circuit arrangement for bus arbitration alters the sequence in which device requests are arbitrated with respect to each other and to a previous arbitration sequence. To this end, an arbiter grants access to a first group of devices according to a predetermined sequen... | 07/03/2008 |
| 20080162770 | HARDWARE VOTING MECHANISM FOR ARBITRATING SCALING OF SHARED VOLTAGE DOMAIN, INTEGRATED CIRCUITS, PROCESSES AND SYSTEMS An electronic circuit includes processors (CPU1, CPU2) operable to make respective voltage requests (Vcpu1, Vcpu2), and a power management circuit (1470) having a controllable supply voltage output (VDD1) is coupled to said proc... | 07/03/2008 |
| 20080133814 | DATA TRANSFER APPARATUS WITH CONTROL OF BUSES TO OPTIMIZE DATA TRANSFER A bus bridge is connected to a primary bus and a secondary bus, and relays data between a master and a target which are each connected to a different one of the primary and secondary buses. The bus bridge includes a primary bus interface, a secondary bus interface, a da... | 06/05/2008 |
| 20080086583 | SOUTH BRIDGE SYSTEM AND METHOD A system including a south bridge, a first processor connected to the south bridge, and a second processor connected to the south bridge. The system further includes at least one device connected to the south bridge, and a resource manager coupled to the south bridge th... | 04/10/2008 |
| 20080034146 | Systems and Methods for Transactions Between Processor and Memory Circuits for improving efficiency and performance of processor-memory transactions are disclosed. One such system includes a processor having a first bus interface unit and a second bus interface unit. The processor can initiate more than one concurrent pending transact... | 02/07/2008 |
| 20080016265 | INFORMATION PROCESSING APPARATUS AND DATA COMMUNICATION DEVICE An information processing apparatus includes a plurality of data communication devices via a high-speed serial bus with a plurality of traffics in different directions present between the data communication devices. A transfer-rate measuring unit measures a transfer rat... | 01/17/2008 |
| 20070271405 | Method for improving bus utilization using predictive arbitration A PCI bridge device includes an arbiter that uses state information comprised of knowledge of the bus protocol and a history of recent transactions to predict the type of transaction a requestor will issue. The prediction is then used as a basis to mask or allow bus req... | 11/22/2007 |
| 20070266196 | Information Processing Apparatus Having Multiple Processing Units Sharing Multiple Resources A technique for improving usage efficiency of a shared resource and improving processing capacity in an information processing apparatus, without increasing the transmission rate or the bit width of a bus is disclosed. Multiple bus interfaces are connected to at least o... | 11/15/2007 |
| 20070220193 | DATA COMMUNICATION CIRCUIT AND ARBITRATION METHOD A statistical-information generating unit monitors packet data output from a transaction layer that constitutes architecture of a PCI Express. The result of the monitored is feedback-controlled to a weight-information updating unit in real time, and is reflected in an a... | 09/20/2007 |
| 20070186026 | System having bus architecture for improving CPU performance and method thereof A system and method for improving the performance of a central processing unit (CPU), in which the system includes a first master such as a CPU, a first local bus connected to a memory device, a bridge, and a main bus connected to a second master and a peripheral device... | 08/09/2007 |
| 20070150637 | Bus systems and method for reconfiguration The invention relates to methods and embodiments of bus systems for configurable architectures. Special consideration is to the optimisation of configuration and reconfiguration efficiency. ... | 06/28/2007 |
| 20070112993 | Data processor A data processor has a first bus master module, first bus slave module and first bus right arbitrating circuit connected to a first bus, a second bus master module, second bus slave module and second bus right arbitrating circuit connected to a second bus, and a bus bri... | 05/17/2007 |
| 20070073954 | Ordering rule and fairness implementation In one embodiment, a controller comprises one or more transaction queues, one or more age counter circuits, and a control circuit. The transaction queues are configured to store a plurality of transaction requests, each having a transaction type. The age counter circuit... | 03/29/2007 |
| 20070073955 | Multi-function PCI device A multi-function peripheral component interconnect (PCI) device is disclosed. The device includes a first configuration data structure associated with a first PCI function, a second configuration data structure associated with a second PCI function and a PCI bridge, cou... | 03/29/2007 |
| 20070011389 | Arbitration method and device In an arbitration device, the entire transfer efficiency is improved without increasing the operating frequency and the number of pins. An overflow monitor mechanism generates an alarm once detecting a danger of occurrence of an overflow in an internal buffer group. An ... | 01/11/2007 |
| 20060282601 | Information processing apparatus and power-saving controlling method According to one embodiment, an information processing apparatus includes a first bridge circuit which communicates with a processor and a storage section, a second bridge circuit which communicates with the first bridge circuit, an external bus control section which co... | 12/14/2006 |
| 20060242351 | Method and apparatus for loading instructions into high memory There is provided a system and method for loading instructions into high memory. Specifically, there is provided a method of operating a computer comprising entering a protected mode before the computer boots a software operating system, and loading instructions stored ... | 10/26/2006 |
| 20060218334 | System and method to reduce memory latency in microprocessor systems connected with a bus A system and method for signaling a deferred response to a data request in a bus connected system is described. In one embodiment, a responding agent on the bus issues a deferred response message when it cannot supply the requested data in a short period of time. When t... | 09/28/2006 |
| 20060190658 | AMBA modular memory controller A system comprising a plurality of controller circuits, a plurality of line buffer circuits and an arbiter. The plurality of control circuits may each be configured to store data. The plurality of line buffer circuits may each be configured to transfer data between an a... | 08/24/2006 |
| 20060161714 | Method and apparatus for monitoring number of lanes between controller and PCI Express device After the initialization of the information processing apparatus, the MMB reads out a value in the Negotiated Link Width register and stores the value in a RAM. When receiving an interrupt from the I/O bridge, the MMB reads out a value in the Negotiated Link Width regis... | 07/20/2006 |
