Bizarre Patents
Decorative Jeweled Wheel Cover
An improved wheel is provided wherein decorative items such as gem stones are embedded in either the wheel surface, a special mounting section attached to the wheel surface, or to a spoke strap that wraps around each spoke and positions embedded gem stones on the outside surface of the spoke.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Application No. | Application Title | Issue Date |
| 20120131251 | FAST AND COMPACT CIRCUIT FOR BUS INVERSION A processor based system with at least one processor, at least one memory controller and optionally other devices having bussed system with a fast and compact majority voter in the circuitry responsible for the bus inversion decision. The majority voter is implemented i... | 05/24/2012 |
| 20120072635 | RELAY DEVICE A relay device includes: an input buffer for receiving data units, each of which includes a header, to which multiple pieces of destination information have been added, and data associated with the header; multiple virtual channels for storing data units, each of the mu... | 03/22/2012 |
| 20120047306 | Bus system and bridge circuit connecting bus system and connection apparatus A bus system includes: a first connection apparatus and a second connection apparatus carrying-out an exchange in accordance with a predetermined protocol; a bus through which the first and second connection apparatuses are connected to each other; and a bridge inserted... | 02/23/2012 |
| 20120036302 | DETERMINATION OF ONE OR MORE PARTITIONABLE ENDPOINTS AFFECTED BY AN I/O MESSAGE A data processing system includes a processor core, a system memory including a first data structure including a plurality of entries mapping requester identifiers (IDs) to partitionable endpoint (PE) numbers, and an input/output (I/O) subsystem including a plurality of... | 02/09/2012 |
| 20120036305 | DETERMINATION VIA AN INDEXED STRUCTURE OF ONE OR MORE PARTITIONABLE ENDPOINTS AFFECTED BY AN I/O MESSAGE A data processing system includes a processor core, a system memory including a first data structure including entries mapping requester identifiers (IDs) to partitionable endpoint (PE) numbers and a second data structure, and an input/output (I/O) subsystem including a... | 02/09/2012 |
| 20120030455 | Information handling system remote input/output connection system An information handling system (IHS) remote input/output (I/O) connection system includes an enclosure having a power button, a communication bus connection point, and an audio connection point. A cable dongle extends from the enclosure. The cable dongle has a first end... | 02/02/2012 |
| 20110320671 | MOVING OWNERSHIP OF A DEVICE BETWEEN COMPUTE ELEMENTS In an embodiment, a command is received that requests movement of ownership of a target device from an origin compute element to a destination compute element. From the origin compute element, a translation of a virtual bridge identifier to a first secondary bus identif... | 12/29/2011 |
| 20110320670 | CONNECTED INPUT/OUTPUT HUB MANAGEMENT A method for implementing connected input/output (I/O) hub configuration and management includes configuring a first I/O hub in wrap mode with a second I/O hub. The hubs are communicatively coupled via a wrap cable. The method further includes generating data traffic on... | 12/29/2011 |
| 20110289248 | Isolated communication bus and related protocol A system includes a master device and multiple slave devices. The system also includes multiple bus interfaces forming a communication bus that couples the master and slave devices. Each bus interface includes a primary interface unit configured to communicate over firs... | 11/24/2011 |
| 20110276739 | INTEGRATED MEMORY CONTROL APPARATUS An integrated memory control apparatus including a first interface decoder, a second interface decoder and an interface controller is provided. Wherein, the first interface decoder is coupled to a control chip through a first serial peripheral interface (SPI), the secon... | 11/10/2011 |
| 20110258359 | SYSTEMS AND METHODS FOR CONDUCTING COMMUNICATIONS AMONG COMPONENTS OF MULTIDOMAIN INDUSTRIAL AUTOMATION SYSTEM An improved industrial automation system and communication system for implementation therein, and related methods of operation, are described herein. In at least some embodiments, the improved communication system allows communication in the form of messages between mod... | 10/20/2011 |
| 20110252174 | HIERARCHICAL TO PHYSICAL MEMORY MAPPED INPUT/OUTPUT TRANSLATION In an embodiment, a translation of a hierarchical MMIO address range to a physical MMIO address range and an identifier of a bridge in a south chip are written to a north chip. A transaction is received that comprises a hierarchical MMIO address. The hierarchical MMIO a... | 10/13/2011 |
| 20110252175 | INTEGRATED MEMORY CONTROL APPARATUS An integrated memory control apparatus including a first interface decoder, a second interface decoder and an interface controller is provided. Wherein, the first interface decoder is coupled to a control chip through a first serial peripheral interface (SPI), the secon... | 10/13/2011 |
| 20110225337 | TRANSACTION PERFORMANCE MONITORING IN A PROCESSOR BUS BRIDGE Described embodiments provide a system having a bridge for connecting two different processor buses. A process monitor within the bridge allows for measuring latency of commands issued on a first bus, passing through the bridge, and executed by clients coupled to the se... | 09/15/2011 |
| 20110208890 | I/O SYSTEMS, METHODS AND DEVICES FOR INTERFACING A PUMP CONTROLLER Embodiments of the present invention provide I/O systems, methods, and devices for interfacing pump controller(s) with control device(s) which may have different interfaces and/or signaling formats. In one embodiment, an I/O interface module comprises a processor, a mem... | 08/25/2011 |
| 20110179211 | BIOS ARCHITECTURE A BIOS architecture adapted in a computer system is provided. The BIOS architecture includes at least one BIOS, a programmable chip module, a baseboard management controller (BMC), a south bridge chip and a network interface controller (NIC). The NIC is connected to the... | 07/21/2011 |
| 20110153898 | VEHICLES INCLUDING BUS-COUPLED HUB UNIT AND POWERTRAIN ELECTRONIC CONTROL UNIT AND METHOD A vehicle includes a body structure, a powertrain, a plurality of sensors, a hub unit, a plurality of leads, a powertrain electronic control unit, and a bus. The powertrain is supported by the body structure and includes an engine and a transmission. Each of the sensors... | 06/23/2011 |
| 20110145629 | FLEXIBLE BUS ARCHITECTURE FOR MONITORING AND CONTROL OF BATTERY PACK The present invention provides a control system which is used for a stacked battery of a plurality of battery packs. Each battery pack has a plurality of battery cells coupled in series. The control system is capable of reconfiguring communication among the battery pack... | 06/16/2011 |
| 20110131359 | PROGRAMMABLE BRIDGE HEADER STRUCTURES A computer system includes compute nodes coupled through a switch to shared or non-shared I/O devices. The switch includes a pool of bridge headers and virtual bridges coupling a root port of a compute node to each of one or more shared or non-shared I/O devices. The sw... | 06/02/2011 |
| 20110125963 | ELECTRONIC DEVICE WITH DATA BACKUP/RESTORE CAPABILITY An electronic device with data backup/restore capability includes a connection port, an internal storage device, a storage device controller, a processor and a bridge circuit. The internal storage device is used for storing data. The storage device controller is coupled... | 05/26/2011 |
| 20110107000 | VOLTAGE INDICATOR SIGNAL GENERATION SYSTEM AND METHOD The present invention provides for a system comprising a peripheral component interface (PCI) host bridge. The PCI host bridge is configured to be coupled to a PCI bus, and to receive a system reset signal, to generate a PCI bus reset signal based on the received system... | 05/05/2011 |
| 20110078473 | LATENCY BASED PLATFORM COORDINATION In some embodiments, an electronic apparatus comprises at least one processor, a plurality of components, and a policy engine comprising logic to receive latency data from one or more components in the electronic device, compute a minimum latency tolerance value from th... | 03/31/2011 |
| 20110072185 | MULTI-PROTOCOL STORAGE DEVICE BRIDGE A bridge includes a host interface via which data/commands are received from and transferred to a host, and a storage device interface via which data/commands are received from and transferred to a storage device. The bridge also includes one SDPC, a controller and a sw... | 03/24/2011 |
| 20110066774 | PROCESSING SYSTEM WITH RF DATA BUS AND METHOD FOR USE THEREWITH A processing system includes a plurality of first circuit modules. A plurality of second circuit modules are coupled to an RF data bus via a 60 GHz communications. The RF data bus receives first data from at least one of the plurality of first circuit modules, and trans... | 03/17/2011 |
| 20110060862 | Systems and Methods for Switchable Memory Configuration Various embodiments of the disclosure provide systems, methods and circuits for implementation and use of a memory system. As one example, a memory system is disclosed that includes a plurality of memory devices and a configuration circuit. The configuration circuit inc... | 03/10/2011 |
| 20110060858 | METHOD FOR ENHANCING PERFORMANCE OF DATA ACCESS BETWEEN A PERSONAL COMPUTER AND A USB MASS STORAGE, ASSOCIATED PERSONAL COMPUTER, AND STORAGE MEDIUM STORING AN ASSOCIATED USB MASS STORAGE DRIVER A method for enhancing performance of data access between a personal computer and a USB Mass Storage is provided. The personal computer is equipped with a plurality of layers of drivers regarding USB data access, and a lower layer of the layers of the drivers includes a... | 03/10/2011 |
| 20110055449 | Logic Chip, Method and Computer Program for Providing a Configuration Information for a Configurable Logic Chip A logic chip has a plurality of individually-addressable resource blocks, each comprising logic circuitry. The logic chip also has a bus comprising a plurality of bus information lines. A first of the resource blocks has a coupling between a first strict sub-set of the ... | 03/03/2011 |
| 20110010522 | MULTIPROCESSOR COMMUNICATION PROTOCOL BRIDGE BETWEEN SCALAR AND VECTOR COMPUTE NODES A multiprocessor computer system includes a plurality of processor nodes coupled by a direct processor interconnect network, and a plurality of processor nodes coupled by an indirect processor interconnect network. A bridge directly couples the direct processor intercon... | 01/13/2011 |
| 20100325333 | Method Allowing Processor with Fewer Pins to Use SDRAM The invention is an apparatus and method to allow a microcontroller unit with fewer pins to use SDRAM. This invention uses the SDRAM burst mode in a favorable way. On an initial cycle of the burst access the microcontroller supplies an address one less than the actual i... | 12/23/2010 |
| 20100306441 | DATA TRANSFER APPARATUS AND DATA TRANSFER METHOD A data transfer apparatus for transferring data between a system bus and a local bus at a high speed is provided. A bus bridge 101 is connected between a system bus 132 and a local bus 137. Data transferred between a CPU 133, an I/O device 12/02/2010 | |
| 20100306430 | BUS CONTROL SYSTEM AND SEMICONDUCTOR INTEGRATED CIRCUIT A bus control circuit includes a first bus to which a first circuit is connected, a second bus to which a second circuit is connected and a control circuit that transfers data between the first circuit and the second circuit, wherein the control circuit monitors complet... | 12/02/2010 |
| 20100287323 | APPARATUS AND METHOD FOR DATA BYPASS FOR A BI-DIRECTIONAL DATA BUS IN A HUB-BASED MEMORY SUB-SYSTEM A memory hub includes first and second link interfaces for coupling to respective data busses, a data path coupled to the first and second link interfaces and through which data is transferred between the first and second link interfaces, and further includes a write by... | 11/11/2010 |
| 20100287318 | I/O AND MEMORY BUS SYSTEM FOR DFPS AND UNITS WITH TWO- OR MULTI-DIMENSIONAL PROGRAMMABLE CELL ARCHITECTURES A general bus system is provided which combines a number of internal lines and leads them as a bundle to the terminals. The bus system control is predefined and does not require any influence by the programmer. Any number of memories, peripherals or other units can be c... | 11/11/2010 |
| 20100281197 | USB BRIDGE A bridge circuit 10 is provided between first data port A1, A2 and second data port B1, B2. The bridge circuit comprises a first transceiver stage 40 comprising at least one input buffer 11, 14 and at least one tri-state ... | 11/04/2010 |
| 20100274942 | CONSTITUTING A CONTROL SYSTEM WITH VIRTUAL AND PHYSICAL BACKPLANES AND MODULES AS BUILDING BLOCKS A custom control system created based on combinations of software applications and hardware control and communication modules overlaid in a virtual backplane. The user can select the modules of interest and map them together without the loss of communications between th... | 10/28/2010 |
| 20100275037 | Low-Power USB SuperSpeed Device with 8-bit Payload and 9-bit Frame NRZI Encoding for Replacing 8/10-bit Encoding A Low-power flash-memory device uses a modified Universal-Serial-Bus (USB) 3.0 Protocol to reduce power consumption. The bit clock is slowed to reduce power and the need for pre-emphasis when USB cable lengths are short in applications. Data efficiency is improved by el... | 10/28/2010 |
| 20100268989 | IMAGE FORMING APPARATUS There is provided an image forming apparatus which adopts a distributed control system and increases the error detection accuracy of each control unit. To accomplish this, the image forming apparatus includes a master control unit that controls the overall image forming... | 10/21/2010 |
| 20100257300 | INTEGRATED MEMORY CONTROL APPARATUS An integrated memory control apparatus including a first interface decoder, a second interface decoder and an interface controller is provided. Wherein, the first interface decoder is coupled to a control chip through a first serial peripheral interface (SPI), the secon... | 10/07/2010 |
| 20100257301 | CONFIGURABLE STORAGE ARRAY CONTROLLER A configurable storage array controller can be configured to either a single-processor configuration or a multi-processor configuration by configuring a data bus switch system.... | 10/07/2010 |
| 20100228902 | KVM SWITCH APPARATUS WITH BRIDGING FUNCTION A KVM switch apparatus with bridging function includes a processor with a keyboard connection interface and a mouse connection interface; a keyboard/mouse switching circuit; a USB bridge unit and at least one computer interface unit electrically connected to at least on... | 09/09/2010 |
