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| Application No. | Application Title | Issue Date |
| 20120084514 | LOCKING A CACHE LINE FOR WRITE OPERATIONS ON A BUS Provided are a computer program product, system, and method for locking a cache line for a burst write operations on a bus. A cache line is allocated in a cache for a target address. A lock is set for the cache line, wherein setting the lock prevents the data in the cac... | 04/05/2012 |
| 20120084071 | Mechanism for NPIV Client Recovery When NPIV Server Goes Down With N_Port ID Virtualization (NPIV), a managed system can be configured so that multiple logical partitions (LPARs) can access independent physical storage through the same physical fibre channel adapter. An NPIV client recovery component of a virtualization management... | 04/05/2012 |
| 20120054750 | POWER-OPTIMIZED INTERRUPT DELIVERY An apparatus, method, system, and computer-readable medium are disclosed. In one embodiment the apparatus is a processor. The processor includes thread remapping logic that is capable of tracking hardware thread interrupt equivalence information for a first hardware thr... | 03/01/2012 |
| 20120047300 | WIRELESS TWO-WAY TRANSMISSION OF SERIAL DATA SIGNALS BETWEEN AN ELECTRONIC DEVICE AND A POWER METER The invention relates to a bidirectional wireless transmission system for serial format data signals between a “master” electronic device (3) and a “slave” energy meter (2) including a microcontroller (20) having a serial input port (RX... | 02/23/2012 |
| 20120047516 | CONTEXT SWITCHING The disclosure relates generally to techniques, methods and apparatus for controlling context switching at a central processing unit. Alternatively, methods and apparatus are provided for providing security to memory blocks. Alternatively, methods and apparatus are prov... | 02/23/2012 |
| 20120047301 | DATA PROCESSOR AND CONTROL SYSTEM Provided are a data processor, and a control system, in which an interrupt controller and an event link controller are adopted. The event link controller responds to a generated event signal to output a start control signal for controlling start of an operation of a cir... | 02/23/2012 |
| 20120042107 | SYSTEM AND METHOD TO INTERRUPT A COMPONENT OF A MOBILE COMMUNICATION DEVICE RESPONSIVE TO A MUTE COMMAND A system and method to interrupt a component of a mobile communication device based on a mute command and a monitored operating condition is disclosed. In another particular embodiment, the method includes receiving a mute command at a mobile communication device while ... | 02/16/2012 |
| 20120036298 | INTERRUPT SOURCE CONTROLLER WITH SCALABLE STATE STRUCTURES A data processing system includes a processor core, a system memory, coupled to the processor core, that includes an interrupt data structure including a plurality of entries each associated with a respective one of a plurality of interrupts. An input/output (I/O) subsy... | 02/09/2012 |
| 20120030392 | System and Method for Automatic Hardware Interrupt Handling A processing system is provided consisting of an interrupt pin, multiple registers, a stack pointer, and an automatic interrupt system. The multiple registers store a number of processor states values. When the system detects an interrupt on the interrupt pin the system... | 02/02/2012 |
| 20120017063 | MECHANISM TO HANDLE PERIPHERAL PAGE FAULTS A page service request is received from a peripheral device requesting that a memory page be loaded into system memory. Page service request information corresponding to the received page service request is written as a queue entry into a queue structure in system memor... | 01/19/2012 |
| 20120017018 | METHOD, SYSTEM, AND APPARATUS FOR COMMUNICATING USING MULTIPLE CONTROLLERS Operating a control system includes repeatedly transmitting a first interrupt to at least one interface unit by a first controller of a plurality of controllers, wherein the first interrupt is transmitted at a first frequency. A first response is received at the first c... | 01/19/2012 |
| 20120005656 | ADAPTER AND DEBUGGING METHOD USING THE SAME A debugging method comprises the steps of: detecting a connecting condition between the target apparatus and the adapter, detecting a connecting condition between the host apparatus and the adapter, comparing a version of BIOS code stored in a firmware of the target app... | 01/05/2012 |
| 20120005300 | SELF CLOCKING INTERRUPT GENERATION IN A NETWORK INTERFACE CARD A network interface card may issue interrupts to a host in which the determination of when to issue an interrupt to the host may be based on the incoming packet rate. In one implementation, an interrupt controller of the network interface card may issue interrupts to th... | 01/05/2012 |
| 20110321015 | HARDWARE TRIGGERING MECHANISM FOR SOFTWARE DEBUGGER Embodiments of the invention utilize a signal analyzer to monitor a data path, the data path to include a plurality of transactions to be executed via a processor. The signal analyzer may further identify data of a first and a second transaction from the plurality of tr... | 12/29/2011 |
| 20110321061 | CONVERTING A MESSAGE SIGNALED INTERRUPTION INTO AN I/O ADAPTER EVENT NOTIFICATION One or more message signaled interruption requests from one or more input/output (I/O) adapters are converted to I/O adapter event notifications. Each I/O adapter event notification includes the setting of one or more specific indicators in system memory and an interrup... | 12/29/2011 |
| 20110320702 | Operation Frequency Adjusting System and Method Techniques pertaining to adjusting the operation frequency of a DRAM are disclosed. According to one embodiment, the DRAM operation frequency adjusting system includes a statistic module counting effective operations of a DRAM to obtain a bandwidth utilization rate of t... | 12/29/2011 |
| 20110314198 | Wireless Peripheral Chips, Host Devices and Multi-Interface Communication Apparatuses A wireless peripheral chip operable to connect to a host device is provided. The wireless peripheral chip includes a first wireless communication module providing a first wireless communication service for the host device and a second wireless communication module provi... | 12/22/2011 |
| 20110307640 | CALL STACK SAMPLING WITH LIGHTWEIGHT THREAD MIGRATION PREVENTION A sample is generated based on an event. Further, an interrupt handler captures information for an interrupted thread on a current processor. In addition, an affinity of the interrupted thread is set such that the interrupted thread runs only on the current processor wi... | 12/15/2011 |
| 20110307641 | Lazy Handling of End of Interrupt Messages in a Virtualized Environment Techniques enable reducing a number of intercepts performed by a hypervisor by reducing a number of End Of Interrupt (EOI) messages sent from a virtual central processing unit (CPU) to a virtual advanced programmable interrupt controller (APIC). The EOI path of the gues... | 12/15/2011 |
| 20110302343 | SYSTEMS AND METHODS FOR PROVIDING INSTANT-ON FUNCTIONALITY ON AN EMBEDDED CONTROLLER Systems and methods for providing instant-on functionality on an embedded controller are disclosed. A method of providing instant-on functionality on a controller comprises an initial state, an intermediate state and a final state. The initial state comprises installing... | 12/08/2011 |
| 20110289242 | MANAGING INTERRUPTS IN A VIRTUALIZED INPUT/OUTPUT DEVICE SUPPORTING MULTIPLE HOSTS AND FUNCTIONS Methods and apparatus are provided for managing interrupts within a virtualizable communication device. Through virtualization, one port of the device may be able to support multiple hosts (e.g., computers) and multiple functions operating on each host. Any number of in... | 11/24/2011 |
| 20110271142 | METHOD AND SYSTEM FOR HANDLING A MANAGEMENT INTERRUPT EVENT IN A MULTI-PROCESSOR COMPUTING DEVICE A method and system for handling a management interrupt, such as a system management interrupt (SMI) and/or a platform management interrupt (PMI), includes allocating two or more processor cores from a plurality of processor cores to form a group of management interrupt... | 11/03/2011 |
| 20110264836 | TECHNIQUES TO MANAGE CRITICAL REGION INTERRUPTS Briefly, techniques to manage interrupts and swaps of threads operating in critical region.... | 10/27/2011 |
| 20110239016 | Power Management in a Multi-Processor Computer System Power management in a multi-processor computer system, including a computer program product for facilitating receiving a task for execution in a high power state, and determining a current power state of a processor in a multi-processor system, the system having a speci... | 09/29/2011 |
| 20110231323 | ENABLEMENT OF LICENSED FEATURES AT A LOGICAL VOLUME LEVEL OF GRANULARITY A licensing application implemented in a computational device receives a request to enable a feature for a logical volume of a plurality of logical volumes controlled by the computational device, wherein each feature of a plurality of features is configurable to be enab... | 09/22/2011 |
| 20110225336 | IMAGE FORMING APPARATUS AND CONTROL METHOD THEREOF An image forming apparatus and a control method thereof. The image forming apparatus includes a plurality of image processors which process an image to be formed on a printing medium corresponding to a plurality of colors, a processor which executes an interrupt routine... | 09/15/2011 |
| 20110202699 | PREFERRED INTERRUPT BINDING A method and system for binding interrupts to central processing units (CPUs). An interrupt controller receives an interrupt that is generated by a device coupled to the computer system. The interrupt controller identifies a preferred CPU associated with the device base... | 08/18/2011 |
| 20110197003 | Interrupt Virtualization In an embodiment, a device interrupt manager may be configured to receive an interrupt from a device that is assigned to a guest. The device interrupt manager may be configured to transmit an operation targeted to a memory location in a system memory to record the inter... | 08/11/2011 |
| 20110185096 | SYSTEMS AND METHODS FOR EMBEDDING INTERRUPTS INTO A SERIAL DATA STREAM Systems and methods for transmitting and processing interrupts by embedding interrupt information into a serial data stream are disclosed. An event is detected and converted into an interrupt signal. The interrupt signal is converted into a special interrupt character o... | 07/28/2011 |
| 20110173360 | SYSTEM AND METHOD OF MONITORING A CENTRAL PROCESSING UNIT IN REAL TIME A method of monitoring one or more central processing units in real time is disclosed. The method may include monitoring state data associated with the one or more CPUs in real-time, filtering the state data, and at least partially based on filtered state data, selectiv... | 07/14/2011 |
| 20110173361 | INFORMATION PROCESSING APPARATUS AND EXCEPTION CONTROL CIRCUIT An information processing apparatus performs switching between an exception handler and normal processing. The information processing apparatus includes a processor; a data processing unit that performs particular processing upon receiving a processing request from the ... | 07/14/2011 |
| 20110161541 | POSTING INTERRUPTS TO VIRTUAL PROCESSORS Embodiments of systems, apparatuses, and methods for posting interrupts to virtual processors are disclosed. In one embodiment, an apparatus includes look-up logic and posting logic. The look-up logic is to look-up an entry associated with an interrupt request to a virt... | 06/30/2011 |
| 20110153561 | MULTI-PHASE FILE SYSTEM RESTORE WITH SELECTIVE ON-DEMAND DATA AVAILABILITY A selective restore technique for restoring file systems within computer systems provides on-demand access during the restore process, while preventing users from slowing the restore process by generating random accesses to files that have not yet been restored, early i... | 06/23/2011 |
| 20110154080 | METHOD AND APPARATUS FOR I/O DEVICES ASSISTED PLATFORM POWER MANAGEMENT Embodiments of an apparatus, system and method are described for input/output (I/O) device assisted platform power management. An apparatus may comprise, for example, power management logic operative to receive idle duration information from one or more input/output (I/... | 06/23/2011 |
| 20110153951 | GLOBAL INSTRUCTIONS FOR SPIRAL CACHE MANAGEMENT A pipelined cache memory and a method of operation support global operations within the cache. The cache may be a spiral cache, with a move-to-front M2F network for moving values from a backing store to a front-most tile coupled to a processor or lower-order level of a ... | 06/23/2011 |
| 20110145634 | APPARATUS, A RECOVERY METHOD AND A PROGRAM THEREOF An apparatus and method for automatically recovering a hardware when the hardware is not accessible from the processing unit. The hardware is recovered via a path different from a path which the processing unit uses when the processing unit fails to access to the hardwa... | 06/16/2011 |
| 20110145203 | METHOD, SYSTEM, AND APPARATUS FOR ARCHIVING NETWORKED DATA A method for archiving networked data includes repeatedly transmitting an interrupt message to at least one controller, wherein each transmission of the interrupt message includes a data collection command, and wherein a portion of the transmissions of the interrupt mes... | 06/16/2011 |
| 20110145457 | APPARATUS AND METHOD FOR MEASURING THE PERFORMANCE OF EMBEDDED DEVICES The apparatus for measuring the performance of embedded devices includes: a transceiver that transmits and receives data to and from the embedded devices; an interrupt generator that generates interrupt signal; a controller that controls the interrupt generator and the ... | 06/16/2011 |
| 20110145458 | METHODS AND SYSTEMS FOR SERVICING INTERRUPTS GENERATED RESPONSIVE TO ACTUATION OF HARDWARE, VIA VIRTUAL FIRMWARE The methods and systems described herein describe methods and systems for forwarding an interrupt that is generated by hardware to virtual firmware executing on a virtual machine. A control program receives an interrupt generated by hardware connected to the computing d... | 06/16/2011 |
| 20110138093 | INTEGRATED CIRCUIT PACKAGE WITH MULTIPLE DIES AND INTERRUPT PROCESSING A package includes a first die and a second die. The dies are connected to each other through an interface. The package includes interrupt processing for detecting interrupt information and providing a packet in response to the interrupt information detection. The packe... | 06/09/2011 |
