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| Application No. | Application Title | Issue Date |
| 20130054849 | UNIFORM MULTI-CHIP IDENTIFICATION AND ROUTING SYSTEM Various methods, computer-readable mediums, articles of manufacture and systems are disclosed. In one aspect, a method is provided that includes generating a packet with a first semiconductor chip. The packet is destined to transit a first substrate and be received by a... | 02/28/2013 |
| 20120254529 | MOTHERBOARD WITH DDR MEMORY DEVICES A motherboard includes a central processing unit (CPU) with a reset signal output pin, a buffer circuit, and at least one memory device. The buffer circuit includes an input terminal connected to the reset signal output pin of the CPU and at least one output terminal. T... | 10/04/2012 |
| 20120246364 | DATA PROCESSING APPARATUS AND DATA PROCESSING METHOD A data processing apparatus may include a data conversion unit that arranges the input data in each transfer data in the conversion unit using one transfer data as one transfer unit and a predetermined number of transfer units as one conversion unit when converting a pl... | 09/27/2012 |
| 20120166827 | Method and Apparatus for Reducing Dynamic Power within System-on-a-Chip Routing Resources A method for saving power in transmission of data across buses. By knowing the power characteristics of a bus and characteristics of data to be transmitted across the bus, the data can be encoded in such a fashion as to conserve system power over transmitting the same d... | 06/28/2012 |
| 20120096211 | PERFORMANCE AND POWER OPTIMIZED COMPUTER SYSTEM ARCHITECTURES AND METHODS LEVERAGING POWER OPTIMIZED TREE FABRIC INTERCONNECT A performance and power optimized computer system architecture and method leveraging power optimized tree fabric interconnect are disclosed. One embodiment builds low power server clusters leveraging the fabric with tiled building blocks while another embodiment impleme... | 04/19/2012 |
| 20120066422 | METHOD AND SYSTEM FOR TRANSFERRING HIGH-SPEED DATA WITHIN A PORTABLE DEVICE A system for high-speed data transfer within a portable device, such as, cell phone or a set-top box, which includes a memory medium and a processor. The system includes a first port for coupling to the processor, and a second port for coupling to the memory medium. Fur... | 03/15/2012 |
| 20120066421 | NETWORK SYSTEM AND NODE A connector unit includes a communication line connecting a receiving port of a physical layer unit of a node to one adjacent node, and a communication line connecting a transmitting port of the physical layer unit to the one adjacent node via a capacitor, and a connect... | 03/15/2012 |
| 20110271063 | SEMICONDUCTOR MEMORY APPARATUS AND DATA INPUT AND OUTPUT METHOD THEREOF A semiconductor memory apparatus includes an input data bus inversion unit configured to determine whether or not to invert a plurality of input data depending upon levels of the plurality of input data, and generate a plurality of conversion data; data input lines conf... | 11/03/2011 |
| 20110225331 | GENERIC INTERFACE A system and process for ensuring the smooth flow of electronic ink is described. Dynamic rendering is given priority over other event handlers. Priority may be the use of one or more queues to order when events occur and may be performing dynamic rendering prior to oth... | 09/15/2011 |
| 20110156872 | SMART RFID READER/ROUTER A smart RFID reader/router is disclosed for connecting RFID readers to a data network. The smart RFID reader/router includes a plurality of connection ports for RFID readers, a plurality of data network ports for connection to a data network, and an internal processor f... | 06/30/2011 |
| 20110161929 | USING AN ENTERPRISE MESSAGING BUS TO AUTOMATICALLY INFLUENCE THE PROCESS OF SOFTWARE COMPILATION AND PACKAGING FOR USE BY A COLLABORATIVE PROJECT A build system executes a build process using an enterprise messaging bus, a plurality of services, and a plurality of shims, where each of the services do not natively communicate with the enterprise messaging bus. A shim processes a message between a service and an en... | 06/30/2011 |
| 20110153883 | DUAL FIELD INSTRUMENT A dual field instrument may include a first microprocessor that includes a first address bus and a first data bus and performs a first operation process, a second microprocessor that includes a second address bus and a second data bus performs a second operation process... | 06/23/2011 |
| 20110153925 | MEMORY CONTROLLER FUNCTIONALITIES TO SUPPORT DATA SWIZZLING A memory controller that can determine a swizzling pattern between the memory controller and memory devices. The memory controller generates a swizzling map based on the determined swizzling pattern. The memory controller may internally swizzle data using the swizzling ... | 06/23/2011 |
| 20110145453 | CAPACITIVE MULTIDROP BUS COMPENSATION The signal integrity of a high speed heavily loaded multidrop memory bus is often degraded due the numerous impedance mismatches. The impedance mismatches causes the bus to exhibit a nonlinear frequency response, which diminishes signal integrity and limits the bandwidt... | 06/16/2011 |
| 20110119408 | METHOD AND SYSTEM FOR CONNECTING A HOST AND MULTIPLE STORAGE DEVICES FORMED BY OPTICAL INTERCONNECTS AND OPTICAL LINK CREATION METHOD A connection scheme for connection from a host or the like to multiple storage devices via an optical link, and in particular to an optical connection scheme or an optical wiring scheme for realizing multiplexing/redundancy by utilizing branches of an optical link and t... | 05/19/2011 |
| 20110099456 | SUPPORTING GLOBAL INPUT/OUTPUT INTERCONNECT FEATURES ON PORTS OF A MIDPOINT DEVICE In a first embodiment of the present invention, a method for operating a midpoint device utilizing an Input/Output (I/O) interconnect is provided, wherein the midpoint device contains a plurality of ports, the method comprising: receiving a request to initiate a session... | 04/28/2011 |
| 20110099308 | SPLIT TRANSACTION PROTOCOL FOR A BUS SYSTEM A method of and apparatus for communicating between a host and an agent. The method includes the step of performing a first transaction between a host controller and a hub. The hub is operable to perform a single transaction with an agent based on the first transaction.... | 04/28/2011 |
| 20110057939 | Reading a Local Memory of a Processing Unit Disclosed herein are systems, apparatuses, and methods for enabling efficient reads to a local memory of a processing unit. In an embodiment, a processing unit includes an interface and a buffer. The interface is configured to (i) send a request for a portion of data in... | 03/10/2011 |
| 20110040911 | DUAL INTERFACE COHERENT AND NON-COHERENT NETWORK INTERFACE CONTROLLER ARCHITECTURE A dual interface coherent and non-coherent network interface controller architecture is generally presented. In this regard, a network interface controller is introduced including a non-coherent bus interface to communicatively couple with devices of a system through a ... | 02/17/2011 |
| 20110034043 | COMMUNICATION WITH A MULTI-CONTACT PAD HAVING A USB APPLICATION Apparatus for making an electrical connection in a system requiring four electrical connections, including an electrical connection pad having an array of four types of electrically conductive contacts, all conductive contacts of a given type being electrically connecte... | 02/10/2011 |
| 20110029709 | Data Movement System and Method Provided is a method of streaming transfer of data between a plurality of devices of a computer system. The method includes providing data to be sent from a source device to a target device and includes receiving, at the source device, one or more transfer credits from ... | 02/03/2011 |
| 20110029702 | METHOD AND APPARATUS PERTAINING TO PORTABLE TRANSACTION-ENABLEMENT PLATFORM-BASED SECURE TRANSACTIONS A portable transaction-enablement platform carries out certain actions to improve the protection of sensitive information. This can comprise detecting when a user of the portable transaction-enablement platform prepares to use the portable transaction-enablement platfor... | 02/03/2011 |
| 20110022752 | METHOD FOR TRANSMITTING DATA IN A CYCLE-BASED COMMUNICATION SYSTEM In a method for transmitting data from a transmitting user of a cycle-based communication system to a receiving user of the communication system, the data are transmitted via a communication medium in messages that repeat in communication cycles and that respectively in... | 01/27/2011 |
| 20110022750 | Interface for Bridging Out-Of-Band Information from a Downstream Communication Link to an Upstream Communication Link A device includes a first interface to receive a signal from a first communication link, wherein the receive signal includes out-of-band (OOB) information. A detector coupled to the first interface detects the OOB information. An encoder coupled to the detector encodes ... | 01/27/2011 |
| 20110010043 | VEHICLE COMMUNICATION SYSTEMS AND METHODS FOR ELECTRIC VEHICLE POWER MANAGEMENT A system and methods that enables enhanced vehicle communications for electric vehicle power management. In an embodiment, a system provides for communications in a power flow management system utilizing existing hardware including a smart charging module. In another em... | 01/13/2011 |
| 20110010475 | METHOD AND DEVICE FOR LOGGING PROCESS VARIABLES OF A DIGITAL FIELD DEVICE A method and an electronic device are provided for logging process variables of a bus-controlled automation system in which process variables which are relevant to evaluation are buffered in at least one digital field device and are subsequently read, for the purpose of... | 01/13/2011 |
| 20100312962 | N-WAY DIRECTLY CONNECTED ANY TO ANY CONTROLLER ARCHITECTURE Disclosed is a storage system architecture. Array controllers are configured with at least 2M ports, where M is an integers greater than two that corresponds to the number of SAS domains or JBOD units in the system. Serial attached SCSI (SAS) domains or JBOD units are c... | 12/09/2010 |
| 20100312921 | LOW POWER PEER DETECTION CIRCUIT Systems and methods are disclosed for detecting the connection of a FireWire peer to a FireWire device. In one embodiment, a device may determine whether a peer connection is present based on peer detection circuit configured in each FireWire port of a FireWire device. ... | 12/09/2010 |
| 20100306501 | Hybrid Computer Systems A hybrid computer system is provided, including first and second computer devices. The first computer device is configured with the second computer device via a connection unit. Each of the first computer device and the second computer device is capable of operating ind... | 12/02/2010 |
| 20100268995 | HARDWARE PROCESS TRACE FACILITY A method for tracing thread bus transactions in a multiprocessor system comprises decoding, by a processor, a first thread instruction of a thread, the thread comprising an ordered series of thread instructions. In the event the first thread instruction is a set bus tra... | 10/21/2010 |
| 20100268053 | Method and Device for Detecting USB Cable Connection Methods, devices, and system including detecting the presence of an electrical connection in a data port of a medical device, the presence of the electrical connection associated with a variation in a signal level resulting from the electrical connection in the data por... | 10/21/2010 |
| 20100262845 | CABLE WITH MEMORY A cable for providing electric power from a power source to a mobile device, the cable having a first connector at a first end of the cable for connecting the cable to a mobile device and with a second connector at a second end for connecting the cable to the power sour... | 10/14/2010 |
| 20100257397 | ACTIVE TRAINING OF MEMORY COMMAND TIMING Embodiments of the invention are generally directed to systems, methods, and apparatuses for the active training of memory command timing. In some embodiments, the CMD/CTL timing is actively trained using active feedback between memory modules and the memory controller.... | 10/07/2010 |
| 20100223427 | SYSTEM FOR HANDLING INPUT/OUTPUT REQUESTS BETWEEN STORAGE ARRAYS WITH DIFFERENT PERFORMANCE CAPABILITIES An apparatus comprising a remote storage array, a primary storage array and a network. The remote storage array may be configured to (i) define a queue size based on a performance capability of the remote storage array, (ii) generate a multiplier based on resources bein... | 09/02/2010 |
| 20100201308 | DEVICE AND METHOD FOR BATTERY CHARGING The invention relates to a method for detecting a charger on a serial data bus in a first device (8). The method comprises connecting (100) said first device to a second device via a serial data bus interface, measuring (104) logic voltage levels of... | 08/12/2010 |
| 20100188917 | Setting Memory Device Termination in a Memory Device and Memory Controller Interface in a Communication Bus A memory device and memory controller are coupled during driver training to reduce mismatches. The impedances of the system are controlled through a termination at the memory device to yield improvements in timing margins. The coupling of the components on a shared elec... | 07/29/2010 |
| 20100188916 | Setting Memory Controller Driver to Memory Device Termination Value in a Communication Bus A method and system are provided for coupling a DRAM and a memory controller during driver training to reduce mismatches by controlling impedances within the system environment. A memory device initializes a bit level voltage on a data net. A driver impedance in a drivi... | 07/29/2010 |
| 20100188918 | Setting Controller VREF in a Memory Controller and Memory Device Interface in a Communication Bus A memory device is connected through an interface to a memory controller. The controller's reference voltage is set based on a driver's impendence of the memory device during driver training. The voltage is applied to a reference resistor pair at the controller and chan... | 07/29/2010 |
| 20100191880 | MEMORY MODULE CAPABLE OF IMPROVING THE INTEGRITY OF SIGNALS TRANSMITTED THROUGH A DATA BUS AND A COMMAND/ADDRESS BUS, AND A MEMORY SYSTEM INCLUDING THE SAME A memory module and a related memory system are disclosed. The memory module comprises a semiconductor memory having a data output buffer, a data input buffer, a command/address input buffer and a first termination resistor unit connected to a data bus. The memory modul... | 07/29/2010 |
| 20100188919 | Calibration of Memory Driver With Offset in a Memory Controller and Memory Device Interface in a Communication Bus A method and system are provided for coupling a DRAM and a memory controller during driver training to reduce mismatches by controlling impedances within the system environment. The memory device, which is typically the device initializing a bit level voltage on a data ... | 07/29/2010 |
