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...Daniel Webster invented a "bull plow" to pull out tree stumps. It didn't catch on because it was huge and required four oxen to pull it!
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| Application No. | Application Title | Issue Date |
| 20120016532 | APPLIANCE INCORPORATING LOAD SELECTIVITY WITHOUT EMPLOYMENT OF SMART METERS Methods and a system are disclosed for one or more appliances including a controller for managing power consumption within a household. The controller is configured to receive and process a signal indicative of one or more energy parameters of an associated energy utili... | 01/19/2012 |
| 20110280495 | Multi-Function Summing Machine A system for processing an image including multiple pixels and intensity data thereof. An image memory is adapted for storing the image. An arithmetic core is connectible to the image memory and adapted for inputting the intensity data. The arithmetic core includes a mu... | 11/17/2011 |
| 20110238721 | ADDER CIRCUIT AND XIU-ACCUMULATOR CIRCUIT USING THE SAME A Xiu-accumulator circuit including N cascaded adders is provided. Each adder includes two registers, wherein one register stores an addition result information and the other register stores a carry-in information. Respective addition result information from respective ... | 09/29/2011 |
| 20110093518 | NEAR OPTIMAL CONFIGURABLE ADDER TREE FOR ARBITRARY SHAPED 2D BLOCK SUM OF ABSOLUTE DIFFERENCES (SAD) CALCULATION ENGINE Embodiments of a near optimal configurable adder tree for arbitrary shaped 2D block sum of absolute differences (SAD) calculation engine are generally described herein. Other embodiments may be described and claimed. In some embodiments, a configurable two-dimensional a... | 04/21/2011 |
| 20110010410 | SYSTEM FOR CONVERGENCE EVALUATION FOR STATIONARY METHOD ITERATIVE LINEAR SOLVERS A system for evaluating the convergence to a solution for a matrix equation comprises at least one reconfigurable computing device such as a field programmable gate array (FPGA), an update storage element, a conversion element, a summation unit, and a comparator. The FP... | 01/13/2011 |
| 20100332578 | Method and apparatus for performing efficient side-channel attack resistant reduction A time-invariant method and apparatus for performing modular reduction that is protected against cache-based and branch-based attacks is provided. The modular reduction technique adds no performance penalty and is side-channel resistant. The side-channel resistance is p... | 12/30/2010 |
| 20100306302 | TECHNIQUE FOR DETERMINING IF A LOGICAL SUM OF A FIRST OPERAND AND A SECOND OPERAND IS THE SAME AS A THIRD OPERAND A system is used to determine if a sum of a first operand and a second operand is the same as a third operand wherein a comparison to the third operand is of variable length. This is particularly useful in a content addressable memory (CAM) where the likelihood of hit i... | 12/02/2010 |
| 20100274831 | COMPUTING DEVICE, CALCULATING METHOD, AND PROGRAM PRODUCT A computing device includes: a deciding unit which, in computation of values of nodes on a lattice in a direction where a value of m representing a horizontal axis coordinate of the lattice increases, decides dummy nodes to be added to m=n−1, so as to enable values of... | 10/28/2010 |
| 20100257594 | INFORMATION PROCESSING APPARATUS AND METHOD, COMMUNICATION APPARATUS AND METHOD, AND INFORMATION PROCESSING SYSTEM An information processing apparatus includes: a register holding a value input thereto; a first communication path through which an addition command is input; a second communication path through which a subtraction command is input; addition means adding a predetermined... | 10/07/2010 |
| 20100241679 | SIGNAL CONVERSION SYSTEMS A signal conversion system includes a compensation module and a conversion module coupled to the compensation module. The compensation module is operable for adjusting a first compensation signal according to a dynamic signal and adding the first compensation signal to ... | 09/23/2010 |
| 20100209896 | VIRTUAL MANIPULATIVES TO FACILITATE LEARNING Embodiments of the invention disclose a virtual manipulative to facilitate math learning. The virtual manipulative comprises a user interface to progressively form one on more columns to hold partial sums or number decompositions to assist a learner in computing a sum.... | 08/19/2010 |
| 20100202605 | METHOD OF OPTIMIZING COMBINATIONAL CIRCUITS A method of simplifying a combinational circuit establishes an initial combinational circuit operable to calculate a set of target signals. A quantity of multiplication operations performed in a first portion of the initial combinational circuit is reduced to create a f... | 08/12/2010 |
| 20100088357 | Systems and Methods for Memory Efficient Signal and Noise Estimation Various embodiments of the present invention provide systems and methods for estimating signal and noise powers in a received signal set. For example, one embodiment of the present invention provides a method for determining signal power and noise power. The method uses... | 04/08/2010 |
| 20100063986 | COMPUTING DEVICE, METHOD, AND COMPUTER PROGRAM PRODUCT In a computing device that calculates a square of an element in a finite field, a vector representation of the element in the finite field is accepted. The vector representation includes a plurality of elements. The computing device performs a multiplication operation o... | 03/11/2010 |
| 20100049779 | SHARED PARALLEL ADDER TREE FOR EXECUTING MULTIPLE DIFFERENT POPULATION COUNT OPERATIONS A shared parallel adder tree for executing multiple different population count operations on a single datum includes a number of carry-save adders (CSAs) and/or half adders (HAs), arranged in rows, where certain CSAs and HAs are dedicated to a single population count op... | 02/25/2010 |
| 20100042903 | RECONFIGURABLE ADDER In one embodiment, a reconfigurable adder has first and second five-bit non-reconfigurable adders and is selectively configurable to operate in a five-bit mode or a ten-bit mode. In five-bit mode, the first non-reconfigurable adder adds first and second messages to gene... | 02/18/2010 |
| 20100030837 | COMBINED ADDER CIRCUIT ARRAY AND/OR PLANE A method of modifying a group of full adder circuits to compute a Boolean function of a set number of input bits, each full adder circuit having first and second data inputs, a data output, a carry input and a carry output, the full adder circuits being interconnected s... | 02/04/2010 |
| 20100030836 | Adder, Synthesis Device Thereof, Synthesis Method, Synthesis Program, and Synthesis Program Storage Medium A conventional multi-input adder has a problem that only either the number of stages of operation blocks or the number of half adders and full adders can be reduced. In order to solve the problem of the prior art, half adders (HA201,... | 02/04/2010 |
| 20100011047 | Hardware-Based Cryptographic Accelerator A system, method, and apparatus for performing hardware-based cryptographic operations are disclosed. The apparatus can include an encryption device with a hardware accelerator having an accumulator, a multiplier circuit, an adder circuit, and a state machine. The state... | 01/14/2010 |
| 20090271465 | CONFIGURABLE HYBRID ADDER CIRCUITRY Hybrid adder circuitry is provided for integrated circuits such as programmable integrated circuits. The hybrid adder may combine the capabilities of multiple adder architectures. Hybrid adders may include carry select and carry ripple adder circuits. The adder circuits... | 10/29/2009 |
| 20090265410 | Packed add-subtract operation in a microprocessor A packed half-word addition and subtraction operation is performed by a microprocessor in parallel upon half-word operands obtained from designated top or bottom half-word locations of designated source registers of a register file and the sum and difference results of ... | 10/22/2009 |
| 20090265405 | Adder for Obtaining Maximum Accumulated Value of Correlation for Mode Detection in Communication System and Adding Method Using the Adder Disclosed are an adder for obtaining a maximum accumulated value of correlation for mode detection in a communication system, and an adding method using the adder. According to the present disclosure, an adder for obtaining a maximum accumulated value of correlation val... | 10/22/2009 |
| 20090259707 | METHOD AND DEVICE FOR FAST CORRELATION CALCULATION The field of the invention is that of the reception of a radionavigation signal originating from a satellite positioning system such as the GPS system. The present invention concerns a method for calculating correlations between a first sequence and a second sequence, s... | 10/15/2009 |
| 20090216826 | GENERALIZED PROGRAMMABLE COUNTER ARRAYS A Generalized Programmable Counter Array (GPCA) is a reconfigurable multi-operand adder, which can be reprogrammed to sum a plurality of operands of arbitrary size. The GPCA is configured to compress the input words down to two operands using parallel counters. Resultin... | 08/27/2009 |
| 20080252334 | ADDING OR SUBTRACTING INPUTS USING A CARRY SIGNAL WITH A FIXED VALUE OF LOGIC 0 A configurable logic device configured to add or subtract inputs using a carry signal with a fixed value of 0 is described. In embodiment(s), inputs are received by a device. The device is configured to add or subtract the inputs using a carry signal that has a fixed va... | 10/16/2008 |
| 20080240462 | PATTERN DETECTION CIRCUITRY A pattern detection circuit detects a pattern in a received bit stream, for example a repetitive 8-bit silence pattern in a stream of digital audio data. Summing circuitry forms during first alternate time periods a sum of a first sequence comprising a predetermined num... | 10/02/2008 |
| 20080183793 | LOGIC CIRCUIT A logic circuit has a decoder converting first input data into a plurality of first bit data having a constant Hamming weight regardless of the Hamming weight of the first input data, a wiring network, and an encoder converting a plurality of second bit data generated b... | 07/31/2008 |
| 20080172381 | METHOD AND SYSTEM FOR CONNECTING SERVICE PROVIDERS WITH SERVICE REQUESTORS A system and method for connecting service providers with service requesters within a social network. The system and method may operate even if the service requestor does not provide any compensation and is not subject to any obligation in return for the service provide... | 07/17/2008 |
| 20080155005 | DTMF LOCKOUT UTILITY USING EPOCH TIME STAMP A method for converting a first time and a first date in a first format to a second time in a second format includes determining a number of seconds that have elapsed between a predetermined date and a beginning of a current year of the first date. The method further in... | 06/26/2008 |
| 20080109507 | SYSTEM AND METHOD FOR PERFORMING AN OPTIMIZED DISCRETE WALSH TRANSFORM A circuit (26) performs a discrete Walsh transform using a reduced set of arithmetic operators. The circuit (26) comprises a first memory component (32), an adder (36), a subtractor (38), a second memory component (40), and a co... | 05/08/2008 |
| 20060277247 | Hybrid arithmetic logic unit Methods and apparatus for improving the efficiency of an arithmetic logic unit (ALU) are provided. The ALU of the invention combines the operation of a single-cycle ALU with the processing speed of a pipelined ALU. Arithmetic operations are performed in two stages: a fi... | 12/07/2006 |
| 20060259536 | Integer transforming device for moving-picture encoder An integer transforming device for a moving-picture compression encoder, associated with the H.264 standard, comprising: a first adding/subtracting stage including pluralities of adders/subtracters to execute addition and subtraction for input data, generating data exte... | 11/16/2006 |
| 20060184605 | Method of forcing 1's and inverting sum in an adder without incurring timing delay A summing circuit for an adder decodes control signals to determine that the result should be manipulated, and generates a half-sum output which is used to produce a manipulated result based on the control signals. The half-sum output is combined with a previous carry b... | 08/17/2006 |
| 20060179103 | System and method for providing a double adder for decimal floating point operations A system for performing decimal floating point addition. The system includes input registers for inputting a first and second operand for an addition operation. The system also includes a plurality of adder blocks, each calculating a sum of one or more corresponding dig... | 08/10/2006 |
| 20060161614 | N-bit constant adder/subtractor An area efficient realization of an N-bit constant coefficient adder/subtractor implemented on FPGAs, utilizing N LUTs with single output generation capability. It includes three inputs from every LUT for addition/subtraction, without any requirement for extra logic for... | 07/20/2006 |
| 20060136543 | Data processing apparatus and method for performing floating point addition A data processing apparatus and method are provided for adding n-bit significands of first and second floating point operands to produce an n-bit result. The data processing apparatus comprises determination logic operable to determine the larger operand of the first an... | 06/22/2006 |
| 20060101108 | Using a leading-sign anticipator circuit for detecting sticky-bit information A method, an apparatus, and a computer program are provided to more efficiently generate a sticky bit in a Floating Point Design. Traditionally, separate ORing logic or OR trees were employed to compress the stick outputs of a normalization shifter into at least one sti... | 05/11/2006 |
| 20060031278 | Multi-value digital calculating circuits, including multipliers Apparatus and method for performing multi-value arithmetic operations are disclosed. Multi-value signals can be added, subtracted and multiplied using a first truth table to generate a residue and a second truth table to generate a carry. Additionally, method and appara... | 02/09/2006 |
| 20060031279 | Highly parallel structure for fast multi cycle binary and decimal adder unit An adder circuit for adding two binary or two decimal operands A and B in which the carries are calculated directly from the input operands A and B without including the plus 6 or minus 6 operations into the carry calculation. For all timing critical functions the reduc... | 02/09/2006 |
| 20060004902 | Reconfigurable circuit with programmable split adder A reconfigurable circuit includes a multiply-accumulator with a programmable pre-adder and also includes a scramble sequence generator. The scramble sequence generator may provide a despreading sequence to control inputs on the programmable pre-adder. ... | 01/05/2006 |
