Did You Know...
...that while attempting to develop a super strong glue, 3M employee Spencer Silver accidentally developed a glue that was so weak it would barely hold two pieces of paper together? However, his colleague Art Fry needed the glue. Fry sang with his church choir and marked the pages of his hymnal with small scraps of paper that often fell out. He used Silver's glue to hold the papers in place. Today we call this invention Post-it Notes.
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| Application No. | Application Title | Issue Date |
| 20120131082 | COMPUTATION OF A REMAINDER BY DIVISION USING PSEUDO-REMAINDERS Methods, computer systems, and computer program products for calculating a remainder by division of a sequence of bytes interpreted as a first number by a second number is provided. A pseudo-remainder by division associated with a first subsequence of the sequence of by... | 05/24/2012 |
| 20120016532 | APPLIANCE INCORPORATING LOAD SELECTIVITY WITHOUT EMPLOYMENT OF SMART METERS Methods and a system are disclosed for one or more appliances including a controller for managing power consumption within a household. The controller is configured to receive and process a signal indicative of one or more energy parameters of an associated energy utili... | 01/19/2012 |
| 20110295921 | Hybrid Greatest Common Divisor Calculator for Polynomials A hybrid greatest common divisor (GCD) calculator analyzes characteristics of polynomials and selects a particular GCD algorithm from multiple available GCD algorithms based on a combination of characteristics of the polynomials. The selected GCD algorithm is then appli... | 12/01/2011 |
| 20110060786 | DEVICE FOR COMPUTING QUOTIENTS, FOR EXAMPLE FOR CONVERTING LOGICAL ADDRESSES INTO PHYSICAL ADDRESSES A device for calculating the quotient q and remainder r of the division (y·k1+x)/k2, wherein k1 and k2 are integers and constant, and wherein x and y are integers. The device comprises a first digital circuit for receiving as... | 03/10/2011 |
| 20100332578 | Method and apparatus for performing efficient side-channel attack resistant reduction A time-invariant method and apparatus for performing modular reduction that is protected against cache-based and branch-based attacks is provided. The modular reduction technique adds no performance penalty and is side-channel resistant. The side-channel resistance is p... | 12/30/2010 |
| 20100185716 | EIGENVALUE DECOMPOSITION APPARATUS AND EIGENVALUE DECOMPOSITION METHOD The present invention provides an eigenvalue decomposition apparatus that can perform processing in parallel at high speed and high accuracy. The eigenvalue decomposition apparatus comprises a matrix dividing portion 14 that repeatedly divides a symmetric tridiag... | 07/22/2010 |
| 20100011039 | Device and method for solving a system of equations A system of equations with a Toeplitz coefficient matrix [T] can be efficiently solved by approximating the coefficient matrix [T] with an approximately Toeplitz coefficient matrix [Tapp] that can be efficiently transformed to a banded form. The system of equ... | 01/14/2010 |
| 20090248770 | METHODS AND APPARATUS FOR REDUCING OR AVOIDING USE OF NON-SHIFT BASED DIVISIONS IN A COMMUNICATIONS DEVICE Methods and apparatus which reduce or completely eliminate non-shift based divisions as part of estimating transmitted symbols and/or generating slicing parameters corresponding to two symbol transmission streams in a wireless communication system are described. A linea... | 10/01/2009 |
| 20090248780 | Polynomial data processing operation A data processing system 2 includes an instruction decoder 22 responsive to polynomial divide instructions DIVL.PN to generate control signals that control processing circuitry 26 to perform a polynomial division operation. The denominato... | 10/01/2009 |
| 20090228353 | QUERY CLASSIFICATION BASED ON QUERY CLICK LOGS Methods are provided for the classification of search engine queries and associated documents based on search engine query click logs. One or more seed documents or queries are provided that contain content that is representative of a category. A query click log contain... | 09/10/2009 |
| 20090216825 | METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR DETECTING ERRORS IN FIXED POINT DIVISION OPERATION RESULTS A method, computer program product and a system for detecting errors in a result of a fixed-point division operation are provided. The method includes: receiving a result of a fixed-point division operation for a dividend and a divisor; performing a first comparison of ... | 08/27/2009 |
| 20090193066 | COMMUNICATION APPARATUS, METHOD OF CHECKING RECEIVED DATA SIZE, MULTIPLE DETERMINING CIRCUIT, AND MULTIPLE DETERMINATION METHOD A dividing unit sets an actual packet length transferred from a packet receiving section to a variable U, and then sets 2α to a variable V. If a positive number determining section determines that a subtraction result of subtracting a remainder N0 07/30/2009 | |
| 20090089346 | Method For Performing A Division Operation In A System A method for performing a division operation in a system includes a) determining an approximate quotient of a numerator value and a denominator value; b) determining an initial error of the approximate quotient; c) determining a quotient adjustment value based on the in... | 04/02/2009 |
| 20090006509 | High-radix multiplier-divider The high-radix multiplier-divider provides a system and method utilizing an SRT digit recurrence algorithm that provides for simultaneous multiplication and division using a single recurrence relation. When A, B, D and Q are fractions (e.g., Q=0.q−1qâˆ... | 01/01/2009 |
| 20080307023 | METHOD AND APPARATUS FOR ADJUSTING REFERENCE FREQUENCY The invention discloses a method for adjusting a reference frequency. First, a training signal is received based on the reference frequency. Then, a target region of the training signal is divided by an original training sequence so that a quotient polynomial is generat... | 12/11/2008 |
| 20080222230 | Multiplier-divider having error offset function A multiplier-divider capable of offsetting errors includes a plurality of multiplication and division units to perform processes and arrangements so that errors generated by signals passing through the multiplier-divider are offset. As a result impact of the errors is r... | 09/11/2008 |
| 20080208947 | METHOD AND APPRATUS FOR EVALUATING VISITORS TO A WEB SERVER Different web pages on a web server are associated with different qualification profiles, each of which is assigned a value by the web-site proprietor. Traffic data hits at the web-site are analyzed to determine which web pages the visitor viewed on the web server. Each... | 08/28/2008 |
| 20080140744 | Dividers The present invention relates to a divider for dividing a dividend by a divisor. The divider includes a subtractor for subtracting the divisor from the dividend to produce a result, storage space with a preliminary answer, and a processor for revising the dividend and p... | 06/12/2008 |
| 20080071850 | METHODS AND APPARATUS FOR EXTRACTING INTEGER REMAINDERS Methods and apparatus to determine a remainder value are disclosed. A disclosed example method involves, during a compilation phase, causing a processor to multiply a dividend value by a first value to generate a second value associated with a product. The first value i... | 03/20/2008 |
| 20070299901 | DIVISION UNIT, IMAGE ANALYSIS UNIT AND DISPLAY APPARATUS USING THE SAME A division unit, an image analysis unit and a display apparatus using the same capable of simplifying the computation of overall average gray scale are provided. The shift-add type of division unit includes a plurality of shift units for shifting an input signal by a di... | 12/27/2007 |
| 20070299903 | Optimized DFT implementation The present invention relates to a method and apparatus for implementing a discrete Fourier transformation (DFT) of a predetermined vector size, wherein at least one DFT module is configured to perform DFTs of a first predetermined number and of a vector size correspond... | 12/27/2007 |
| 20070299902 | Sparse tree adder Embodiments disclosed herein provide sparse adder circuits comprising Ling type propagate and generate circuits and sparse carry circuits to efficiently add first and second operands to one another.... | 12/27/2007 |
| 20070244956 | Digital computation method involving euclidean division A computational method for implementation in an electronic digital processing system performs integer division upon very large (multi-word) operands. An approximated reciprocal of the divisor is obtained by extracting the two most significant words of the divisor, addin... | 10/18/2007 |
| 20070233774 | Rounding of binary integers Methods and apparatus to provide rounding of a binary integer are described. In one embodiment, a value that indicates whether a divisor divides a binary integer is extracted from a product of the binary integer and a scaled approximate reciprocal of the divisor. ... | 10/04/2007 |
| 20060294177 | Method, system and apparatus of performing division operations Embodiments of the present invention provide a method, apparatus and system of dividing a first number by a second number. Some demonstrative embodiments include generating a first value relating to the first number; generating a second value corresponding to a remainde... | 12/28/2006 |
| 20060242220 | Hardware divider Systems and methods are provided for dividing two digital values. A look-up table provides a first output value in response to a value of an input signal. The first output value corresponds to a first estimate of a reciprocal for the value of the input signal. An approx... | 10/26/2006 |
| 20060224657 | Method, system and apparatus for quotient digit generation Embodiments of the present invention provide a method, apparatus and system to generate a quotient digit corresponding to a quotient of a cycle of a division operation by applying a predetermined criterion to a plurality of expected partial remainder values related to a... | 10/05/2006 |
| 20060173949 | Division arithmatic unit of variable radix A variable radix divider uses dividend, divisor and quotient as division operators and includes an adder/subtractor having inputs of the dividend and the divisor. The divider further includes a first and second quotient/radix generator having inputs of the dividend and ... | 08/03/2006 |
| 20060161613 | Method and apparatus for arithmatic operation of processor A method and apparatus for arithmetic operation of a processor are disclosed. The method and apparatus divide operands whose wordlength is greater than the wordlength which can be processed by a processor once into wordlengths which can be processed by the processor and... | 07/20/2006 |
| 20060136542 | Division algorithm According to an aspect of the present invention, a quotient of a dividend divided by a divisor may be determined after reducing the dividend, divisor, and the remainder by using operations such as add, subtract, multiply, shift, AND which may result in reduced processor... | 06/22/2006 |
| 20060129625 | Low latency integer divider and integration with floating point divider and method A method and device divides a dividend by a divisor, the dividend and the divisor both being integers. The method and device determine a maximum possible number of quotient digits (NDQ) based on a number of significant digits of the divisor and the dividend, normalizes ... | 06/15/2006 |
| 20060129624 | Method and apparatus for performing a divide instruction An apparatus and method to perform a division algorithm on an integer divisor and integer dividend. More particularly, embodiments of the invention relate to a technique to align integer operands such that a relatively fast division algorithm may be performed on the int... | 06/15/2006 |
| 20050289209 | Method and system of achieving integer division by invariant divisor using N-bit multiply-add operation An integer division system for a dividend and a divisor includes a pre-calculation module to select a reciprocal approximation and a rounding error compensation value of the divisor, and an instruction generation module to generate at least an instruction to calculate a... | 12/29/2005 |
| 20050278407 | Addressing type of asynchronous divider The present invention relates to an addressing type of asynchronous divider that uses addressing system, which enables an external circuit to receive a divisor and a dividend. Through the process of addressing type of asynchronous divider, the calculated quotient and re... | 12/15/2005 |
| 20050149597 | Device and method for converting a term A device for converting a term comprising a product of a first operand and a second operand into a representation having an integer quotient regarding a modulus and a remainder, the integer quotient being defined by T/N, T being the term and N being the modulus, and the... | 07/07/2005 |
| 20050038845 | Device and method for calculating a result of a division A device for calculating a result or an integer multiple of the result of a division of a numerator by a denominator includes a unit for providing a factor which is selected such that a product of the factor and the denominator is greater than the result. The device fur... | 02/17/2005 |
| 20050027776 | Method and apparatus for efficient derivation of modulo arithmetic for frequency selection A method and apparatus for efficiently deriving modulo arithmetic solutions for frequency selection in transceivers. A frequency for communication between a wireless user interface device and a wirelessly enabled host is generated by calculating a modulo solution for an... | 02/03/2005 |
| 20050027775 | Methods and apparatus for extracting integer remainders Methods and apparatus for determining a remainder value are disclosed. The methods and apparatus extracts a residuary subset bitfield value from a binary value that is calculated using a scaled approximate reciprocal value that is associated with a compound exponent sca... | 02/03/2005 |
