Class 708/625 - Binary

Subclass of Class 708 - Electrical computers: arithmetic processing and calculating
Definition: Subject matter wherein the numerical digits are of radix
No. of applications: 31
Last issue date: 11/24/2011

Application No.	Application Title	Issue Date
20110289131	MACHINE DIVISION Techniques are generally described that include methods, devices, systems and/or apparatus for dividing a numerator by a denominator. Some example methods may include selecting a first numerical factor stored in an electronic storage media. The first numerical factor ma...	11/24/2011
20110246119	PROCESS FOR TESTING THE RESISTANCE OF AN INTEGRATED CIRCUIT TO A SIDE CHANNEL ANALYSIS A process for testing an integrated circuit includes collecting a set of points of a physical property while the integrated circuit is executing a multiplication, dividing the set of points into a plurality subsets of lateral points, calculating an estimation of the val...	10/06/2011
20100325188	PROCESSOR AND METHOD FOR IMPLEMENTING INSTRUCTION SUPPORT FOR MULTIPLICATION OF LARGE OPERANDS A processor including instruction support for implementing large-operand multiplication may issue, for execution, programmer-selectable instructions from a defined instruction set architecture (ISA). The processor may include an instruction execution unit comprising a h...	12/23/2010
20100306293	Galois Field Multiplier A Galois field multiplier is provided, comprising a multiplication circuit for inputting two m bits binary multiplicators and outputting their product, wherein m is an integral power of 2, and the output of said multiplication circuit is consisted of a high bits portion...	12/02/2010
20100198895	Digital Signal Processor Having Instruction Set With A Logarithm Function Using Reduced Look-Up Table A digital signal processor is provided having an instruction set with a logarithm function that uses a reduced look-up table. The disclosed digital signal processor evaluates a logarithm function for an input value, x, by decomposing the input value, x, to a first part,...	08/05/2010
20100191787	Sequential Multiplier A sequential multiplier for multiplying a binary multiplier and a binary multiplicand to produce a final product. A first logic circuit generates a control signal based on the multiplier. A second logic circuit generates a partial product based on the control signal and...	07/29/2010
20100153830	CARRY BUCKET-AWARE MULTIPLICATION An apparatus comprising an integrated circuit configured to accept a plurality of operands; multiply the operands producing an result in a first binary format; and distribute the result in the first binary format over a plurality of data units in a second binary format,...	06/17/2010
20100057824	METHOD AND SYSTEM FOR PROCESSING THE BOOTH ENCODING 33RD TERM A computer system for computing a binary operation involving a first term multiplied by a second term resulting in a product, where the product is conditionally added to a third term in a central processing unit. The central processing unit includes a carry save adder c...	03/04/2010
20100005131	Power-residue calculating unit and method of controlling the same A power-residue calculating unit according to one embodiment of the present invention includes a multiplication residue calculating unit performing a multiplication calculation and a residue calculation based on a multiplicand, a multiplier, and a divisor, a power stori...	01/07/2010
20090234900	Multi-Value Digital Calculating Circuits, Including Multipliers Apparatus and method for performing multi-value arithmetic operations are disclosed. Multi-value signals can be added, subtracted and multiplied using a first truth table to generate a residue and a second truth table to generate a carry. Additionally, method and appara...	09/17/2009
20090136022	Method and Apparatus for Calculating a Polynomial Multiplication, In Particular for Elliptic Curve Cryptography Safeguarding communication channels is required in particular in wireless networks. The use of encryption mechanisms in the form of software is limited by the required calculation and energy capacities of mobile terminals. Costs are of significance when using hardware s...	05/28/2009
20090132630	METHOD AND APPARATUS FOR MULTIPLYING BINARY OPERANDS Method and apparatus for multiplying a signed first operand na bits and a signed second operand nb bits, wherein na and nb are different positive integer numbers, the method comprising generating single bit products of pairs of a single bit from the signed first operand...	05/21/2009
20090083360	Shift-add based parallel multiplication A system for performing parallel multiplication on a plurality of factors. In a binary processor, a first and a second memory have pluralities of bit-positions. The first memory holds a first value as a multiplier that will commonly serve as multiple of the factors, and...	03/26/2009
20090006517	UNIFIED INTEGER/GALOIS FIELD (2m) MULTIPLIER ARCHITECTURE FOR ELLIPTIC-CURVE CRYTPOGRAPHY A unified integer/Galois-Field 2^mmultiplier performs multiply operations for public-key systems such as Rivert, Shamir, Aldeman (RSA), Diffie-Hellman key exchange (DH) and Elliptic Curve Cryptosystem (ECC). The multiply operations may be performed on prime f...	01/01/2009
20080256164	METHODS AND APPARATUS FOR CARRY GENERATION IN A BINARY LOOK AHEAD SYSTEM Methods and apparatus provide for a carry generation tree for a carry look-ahead binary adder, which includes N stages of operators, reducers, and/or repeaters, wherein: a first of the stages receives binary outputs from a series of binary adders; a last of the stages p...	10/16/2008
20080222227	Design Structure for a Booth Decoder A design structure for a Booth decoder is provided. The Booth decoder may comprise three circuits that run in parallel. A first circuit is used to generate a shift control signal output. A second circuit is used to generate a zero control signal output. A third circuit ...	09/11/2008
20080077647	Parameterized VLSI Architecture And Method For Binary Multipliers Systems and methods of multiplying binary numbers are disclosed. In one such system there is a Sigma unit and an Omega unit. The Sigma unit may generate partial sums of the multiplier and shifted forms of the multiplier. The Omega unit may have a plurality of control un...	03/27/2008
20080063189	OPTIMAL SIGNED-DIGIT RECODING FOR ELLIPTIC CURVE CRYPTOGRAPHY An apparatus and method is described of reducing joint weight for integers involved in a scalar multiplication, such as during cryptography. By way of example, the method is utilized within elliptic curve cryptography (ECC), wherein reducing joint weight speeds the exec...	03/13/2008
20070233773	MODULAR BINARY MULTIPLIER FOR SIGNED AND UNSIGNED OPERANDS OF VARIABLE WIDTHS A system for binary multiplication in a superscalar processor includes a first pipeline, an execution unit, and a first multiplexer; a first rotator in communication with one register of the first pipeline and the execution unit; and a leading zero detection register in...	10/04/2007
20070233772	Modular multiplication acceleration circuit and method for data encryption/decryption A system to process multiplier X and multiplicand Y may include multiplication of a least-significant bit of X and a least-significant w bits of Y to generate a least-significant w bits of product Z. The system may further include determination of whether a least-signif...	10/04/2007
20070214205	MODULAR BINARY MULTIPLIER FOR SIGNED AND UNSIGNED OPERANDS OF VARIABLE WIDTHS A method of implementing binary multiplication in a processing device includes obtaining a multiplicand and a multiplier from a storage device; in the event the multiplier is larger than a selected length, partitioning the multiplier into a plurality of multiplier subgr...	09/13/2007
20070174379	Pre-saturating fixed-point multiplier A pre-saturating multiplier inspects the operands to a multiply operation prior to performing any multiplication. If the operands will cause an overflow requiring saturation, the multiplier outputs the saturated value without multiplying the original operands. In one em...	07/26/2007
20060235922	Quisquater Reduction A method and apparatus for calculating the product P of a first number X and a second number Y, modulo N, where Y is partitioned into j words each of length p bits, and has a length (m+n) bits, cyclically operates on successive ones of the j words of Y, carrying out int...	10/19/2006
20060230094	Digital signal processing circuit having input register blocks An integrated circuit that includes a digital signal processing element (DSPE) having a first and a second register block coupled to a first arithmetic logic unit (ALU) circuit; a middle DSPE adjacent to the top DSPE having a third and a fourth register block coupled to...	10/12/2006
20060117081	Data processing apparatus and method for performing floating point multiplication A data processing apparatus and method are provided for multiplying first and second n-bit significands of first and second floating point operands to produce an n-bit result. The data processing apparatus comprises multiplier logic for multiplying the first and second ...	06/01/2006
20060117082	Data processing apparatus and method for performing floating point multiplication A data processing apparatus and method are provided for multiplying first and second n-bit significands of first and second floating point operands to produce an n-bit result. Multiplier logic is used to multiply the first and second n-bit significands to produce a pair...	06/01/2006
20060117080	Data processing apparatus and method for performing floating point multiplication A data processing apparatus and method are provided for multiplying first and second n-bit significands of first and second floating point operands to produce an n-bit result. The data processing apparatus comprises multiplier logic operable to multiply the first and se...	06/01/2006
20050223054	Multiplier sign extension method and architecture A multiplier sign extension method and architecture are used for encoding operations of a multiplier of a digital signal processor. The multiplier sign extension method comprises the steps of: determining the width of the multiplier to obtain a sign extension bit total ...	10/06/2005
20050198093	Montgomery modular multiplier In a Montgomery multiplier, a modulus product generator may select a modulus product from a plurality of selectable n-bit modulus numbers M, a given modulus number M being formed from a currently input extended chunk of bits among the n-bit modulus numbers. A partial pr...	09/08/2005
20050182814	Encoder for a multiplier An encoder of a multiplier may include an operator generating unit for encoding a plurality of received multiplier data to output a plurality of operators. The encoder may include a partial-product data generating unit that generates a sign selecting operator from the r...	08/18/2005
20050144217	Low-error fixed-width modified booth multiplier A low-error fixed-width multiplier receives a W-bit input and produces a W-bit product. In an embodiment, a multiplier (Y) is encoded using modified Booth coding. The encoded multiplier (Y) and a multiplicand (X) are processed together to generate partial products. The ...	06/30/2005

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Class 708/625 - Binary