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| Application No. | Application Title | Issue Date |
| 20120030267 | Performing Multiplication for a Multi-Channel Notch Rejection Filter A system for processing sample sequences, that may include an input, a sequence of coupled registers, including an accumulator register, and first circuitry that may be coupled to the accumulator register and to the input. The input may be configured to receive a first ... | 02/02/2012 |
| 20110289131 | MACHINE DIVISION Techniques are generally described that include methods, devices, systems and/or apparatus for dividing a numerator by a denominator. Some example methods may include selecting a first numerical factor stored in an electronic storage media. The first numerical factor ma... | 11/24/2011 |
| 20110231468 | HIGH-RADIX MULTIPLIER-DIVIDER The high-radix multiplier-divider provides a system and method utilizing an SRT digit recurrence algorithm that provides for simultaneous multiplication and division using a single recurrence relation. When A, B, D and Q are fractions (e.g., Q=0·q−1 q... | 09/22/2011 |
| 20110225220 | Montgomery Multiplication Architecture A Montgomery multiplication device calculates a Montgomery product of an operand X and an operand Y with respect to a modulus M and includes a plurality of processing elements. In a first clock cycle, two intermediate partial sums are created by obtaining an input of le... | 09/15/2011 |
| 20110103578 | SYSTEMS AND METHODS FOR EFFICIENTLY CREATING DIGESTS OF DIGITAL DATA Systems and methods efficiently process digests, hashes or other results by performing multiplicative functions in parallel with each other. In various embodiments, successive processing stages are provided, with each stage performing parallel multiplicative functions a... | 05/05/2011 |
| 20110060781 | Systems and Methods for Performing Fixed-Point Fractional Multiplication Operations in a SIMD Processor Systems and methods for performing multiplication of fixed-point fractional values with the same throughput as addition and subtraction operations, and without loss of accuracy in the result. In one embodiment, a method includes reading data from a pair of source regist... | 03/10/2011 |
| 20110060780 | SYSTEMS, METHODS, AND APPARATUS FOR CALIBRATING, CONTROLLING, AND OPERATING A QUANTUM PROCESSOR Quantum annealing may include applying and gradually removing disorder terms to qubits of a quantum processor, for example superconducting flux qubits of a superconducting quantum processor. A problem Hamiltonian may be established by applying control signals to the qub... | 03/10/2011 |
| 20100325188 | PROCESSOR AND METHOD FOR IMPLEMENTING INSTRUCTION SUPPORT FOR MULTIPLICATION OF LARGE OPERANDS A processor including instruction support for implementing large-operand multiplication may issue, for execution, programmer-selectable instructions from a defined instruction set architecture (ISA). The processor may include an instruction execution unit comprising a h... | 12/23/2010 |
| 20100318592 | Multiplicative Division Circuit With Reduced Area The technology is a division circuit with decreased circuit area. An embodiment includes an integrated circuit implementing multiplicative division of a dividend input and a divisor input. The integrated circuit includes a lookup table circuit and multiplier circuits. T... | 12/16/2010 |
| 20100306298 | DEVICE FOR DFT CALCULATION A device to perform DFT calculations, for example in a GNSS receiver, including two banks of multipliers by constant integer value, the values representing real and imaginary part of twiddle factors in the DFT. A control unit selectively routes the data through the appr... | 12/02/2010 |
| 20100306292 | DSP Engine with Implicit Mixed Sign Operands A processor may have at least one multiplier unit which can be controlled to operate in a signed, an unsigned, or a mixed sign mode; a multiplier unit mode decoder coupled with the multiplier unit which receives location information of a first and second operands, where... | 12/02/2010 |
| 20100228806 | MODULAR DIGITAL SIGNAL PROCESSING CIRCUITRY WITH OPTIONALLY USABLE, DEDICATED CONNECTIONS BETWEEN MODULES OF THE CIRCUITRY Digital signal processing (“DSP”) circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilita... | 09/09/2010 |
| 20100205234 | METHOD AND APPARATUS FOR DETECTING SIGNAL USING CYCLO-STATIONARY CHARACTERISITICS A method and apparatus for detecting a signal using a cyclo-stationary characteristic value is provided. A method of detecting a signal using a cyclo-stationary characteristic value includes: calculating cyclo-stationary characteristic values with respect to a cyclic fr... | 08/12/2010 |
| 20100202605 | METHOD OF OPTIMIZING COMBINATIONAL CIRCUITS A method of simplifying a combinational circuit establishes an initial combinational circuit operable to calculate a set of target signals. A quantity of multiplication operations performed in a first portion of the initial combinational circuit is reduced to create a f... | 08/12/2010 |
| 20100198894 | Digital Signal Processor Having Instruction Set With An Exponential Function Using Reduced Look-Up Table A digital signal processor is provided having an instruction set with an exponential function that uses a reduced look-up table. The disclosed digital signal processor evaluates an exponential function for an input value, x, by decomposing the input value, x, to an inte... | 08/05/2010 |
| 20100198893 | Digital Signal Processor Having Instruction Set With An Xk Function Using Reduced Look-Up Table A digital signal processor is provided having an instruction set with an xK function that uses a reduced look-up table. The disclosed digital signal processor evaluates an xK function for an input value, x, by computing Log(x) in hardware; multiply... | 08/05/2010 |
| 20100191788 | Multiplier with Shifter A digital system has a memory configured to hold operands and a multiply-shift unit coupled to the memory and configured to receive a first operand and a second operand from the memory in parallel, wherein the first operand includes a concatenated encoded shift amount. ... | 07/29/2010 |
| 20100125621 | ARITHMETIC PROCESSING DEVICE AND METHODS THEREOF An arithmetic processing unit is disclosed that can perform multiply operations, addition operations, or a combination thereof. The arithmetic processing unit can operate in two modes. The first mode supports one single, double, or extended-precision computation, and th... | 05/20/2010 |
| 20100125620 | ARITHMETIC PROCESSING DEVICE AND METHODS THEREOF A device and methods are disclosed for communicating an unrounded result from one arithmetic calculation for use in a second, subsequent calculation. For example, an unrounded result of a first calculation can be forwarded to provide a multiplier, a multiplicand or an a... | 05/20/2010 |
| 20100088357 | Systems and Methods for Memory Efficient Signal and Noise Estimation Various embodiments of the present invention provide systems and methods for estimating signal and noise powers in a received signal set. For example, one embodiment of the present invention provides a method for determining signal power and noise power. The method uses... | 04/08/2010 |
| 20100063986 | COMPUTING DEVICE, METHOD, AND COMPUTER PROGRAM PRODUCT In a computing device that calculates a square of an element in a finite field, a vector representation of the element in the finite field is accepted. The vector representation includes a plurality of elements. The computing device performs a multiplication operation o... | 03/11/2010 |
| 20100023569 | METHOD FOR COMPUTERIZED ARITHMETIC OPERATIONS A method of computing arithmetic operations more efficiently than the conventional Arithmetic Logic Unit (ALU) is disclosed. By encoding both operands from Binary Coded Decimal (BCD) codes (0000, to 1001) into decimal digits (0 to 9), inputting them in the GerTh's™ lo... | 01/28/2010 |
| 20100011047 | Hardware-Based Cryptographic Accelerator A system, method, and apparatus for performing hardware-based cryptographic operations are disclosed. The apparatus can include an encryption device with a hardware accelerator having an accumulator, a multiplier circuit, an adder circuit, and a state machine. The state... | 01/14/2010 |
| 20090254333 | LFSR Emulation Apparatus for emulating the operation of an LFSR having at least one of one or more inputs and one or more outputs, wherein the state of the LFSR can be described by a state vector having sections describing the input or inputs, if any, of the LFSR, the contents of the ... | 10/08/2009 |
| 20090248769 | Multiply and accumulate digital filter operations A multiply and accumulate engine may implement a digital filter. In some embodiments, the number of coefficients that are stored may be equal to only half of the number of filter taps that are implemented. This may be done by doing multiplications operand by operand wit... | 10/01/2009 |
| 20090228538 | MULTI INPUT CODING ADDER, DIGITAL FILTER, SIGNAL PROCESSING DEVICE, SYNTHESIZER DEVICE, SYNTHESIZING PROGRAM, AND SYNTHESIZING PROGRAM RECORDING MEDIUM Conventional multi-input multiplication and addition circuit having fixed multipliers has problems in that when the number of inputs increases, the number of partial product generator circuits would increase, and also the number of stages of the addition blocks would in... | 09/10/2009 |
| 20090172067 | METHODS AND APPARATUS FOR IMPLEMENTING A SATURATING MULTIPLIER Methods and apparatus are provided for implementing an efficient saturating multiplier associated with addition and subtraction logic. The result of the multiplier is saturated before accumulating. The result of the multiplier can be stored in a result register in unsat... | 07/02/2009 |
| 20090164546 | METHOD AND APPARATUS FOR EFFICIENT PROGRAMMABLE CYCLIC REDUNDANCY CHECK (CRC) A method and apparatus to optimize each of the plurality of reduction stages in a Cyclic Redundancy Check (CRC) circuit to produce a residue for a block of data decreases area used to perform the reduction while maintaining the same delay through the plurality of stages... | 06/25/2009 |
| 20090157790 | METHOD AND APPARATUS FOR MULTIPLYING POLYNOMIALS WITH A PRIME NUMBER OF TERMS An efficient method and apparatus to compute a product of polynomials of degree n−1 where n is an arbitrary prime is provided. The total number of multiply operations and Arithmetic Logical Unit (ALU) operations to compute the product is minimized through the judiciou... | 06/18/2009 |
| 20090157789 | Multiplicative Group Counter Systems and methods are provided for efficiently counting detected events via a multiplicative group counter. An equivalent class polynomial congruent with a first of a plurality of elements comprising a multiplicative group is represented as a series of binary values. ... | 06/18/2009 |
| 20090146691 | LOGIC CELL ARRAY AND BUS SYSTEM A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus ele... | 06/11/2009 |
| 20090138744 | MULTIPLIER DEVICE WITH SUPPRESSION OF HIGHER-ORDER DISTORTION A multiplier device is configured to include first to nth multipliers M1 to Mn for multiplying a carrier modulated information signal with first to nth mutually phase shifted and identical, substantially square wave mixing sig... | 05/28/2009 |
| 20090125576 | Pade approximation convert circuit of direct digital frequency synthesizer This invention relates to Pade approximation convert circuit of the direct digital frequency synthesizer in which a multiplier receives and multiplies a first input signal and a variable signal so as to produce a multiplication signal; a divider receives and divides a s... | 05/14/2009 |
| 20090003695 | METHOD AND CIRCUIT FOR CORRECTING SIGNALS AND IMAGE CORRECTING METHOD AND CIRCUIT USING THE SAME A signal correcting method and a circuit thereof are provided. In the method, first, the values of a plurality of input signals are clamped to generate a plurality of corresponding clamping signals according to a plurality of adjustable predetermined values. Then, a com... | 01/01/2009 |
| 20090006509 | High-radix multiplier-divider The high-radix multiplier-divider provides a system and method utilizing an SRT digit recurrence algorithm that provides for simultaneous multiplication and division using a single recurrence relation. When A, B, D and Q are fractions (e.g., Q=0.q−1q... | 01/01/2009 |
| 20080275932 | Integer Division In A Manner That Counters A Power Analysis Attack In the course of performing an Elliptic Curve Scalar Multiplication operation by Additive Splitting Using Division, a main loop of an integer division operation may be performed. The integer division has a dividend and a divisor. By storing both the divisor and the nega... | 11/06/2008 |
| 20080225939 | MULTIFUNCTIONAL VIDEO ENCODING CIRCUIT SYSTEM The present invention discloses a multifunctional video encoding circuit system capable of performing six types of operations: addition, subtraction, multiplication, multiply-accumulation, interpolation, and absolute difference summation. A partial product generation pa... | 09/18/2008 |
| 20080222226 | Bandwidth efficient instruction-driven multiplication engine Multiplication engines and multiplication methods are provided for a digital processor. A multiplication engine includes multipliers, each receiving a first operand and a second operand; a local operand register having locations to hold the first operands for respective... | 09/11/2008 |
| 20080208940 | RECONFIGURABLE CIRCUIT A reconfigurable circuit including a multiplier for multiplying a value, an accumulator for cumulatively adding said multiplied value and a round-off processing unit for rounding off said cumulatively added value; wherein said multiplier, said accumulator and said round... | 08/28/2008 |
| 20080144812 | Method for performing iterative scalar multiplication which is protected against address bit attack The system and method for performing iterative scalar multiplication which is protected against address bit attack is provides a methodology, and system for implementing the methodology, for performing an iterative scalar multiplication process utilizing the Takagi algo... | 06/19/2008 |
