Did You Know...
...that the Slinky toy was the result of a failed attempt by engineer Richard James to produce an antivibration device for ship instruments? His goal was to develop a spring that would instantaneously counterbalance the wave motion that rocks a ship at sea. Instead, he developed the Slinky.
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| Application No. | Application Title | Issue Date |
| 20110078225 | Extended-Precision Integer Arithmetic and Logical Instructions The invention set forth herein describes a mechanism for efficiently performing extended precision operations on multi-word source operands. Corresponding data words of the source operands are processed together via each instruction of a cascading sequence of instructio... | 03/31/2011 |
| 20110040816 | Negative two's complement processor for windowing in harmonic analysis The present invention provides a solution to the shortcomings of the traditional two's complement system that is commonly utilized in modern computing systems and digital signal processors for calculating harmonic analysis using a discrete time-frequency transform. In t... | 02/17/2011 |
| 20110004644 | DYNAMIC FLOATING POINT REGISTER PRECISION CONTROL Apparatus and methods are provided to perform floating point operations that are adaptive to the precision formats of input operands. The apparatus includes adaptive conversion logic and a tagged register file. The adaptive conversion logic receives the input operands, ... | 01/06/2011 |
| 20100257221 | Packed restricted floating point representation and logic for conversion to single precision float An apparatus for expanding an immediate vector of restricted data structures may include logic connected to a first memory and a second memory connected to the logic. The first memory may store the immediate vector of restricted data structures that specify distinct flo... | 10/07/2010 |
| 20100235416 | MECHANISM FOR FAST DETECTION OF OVERSHIFT IN A FLOATING POINT UNIT OF A PROCESSING DEVICE A floating point unit includes a floating point adder to perform a floating point addition operation between first and second floating point numbers each having an exponent and a mantissa. The floating point unit also includes an alignment shifter that may calculate a s... | 09/16/2010 |
| 20100198901 | Managing Floating Point Variables in Constraint Satisfaction Problems Systems and methods for managing floating point variables are described in the present disclosure. According to one example, an embodiment of a method includes analyzing a constraint on a floating point variable in a system that supports both floating point variables an... | 08/05/2010 |
| 20100169605 | ARBITRARY PRECISION FLOATING NUMBER PROCESSING Techniques for providing arbitrary precision floating number (APFN) processing are disclosed. In some aspects, an APFN store may be used to store a large number (i.e., an APFN) having many significant digits, which in turn may enable a high degree of precision in mathem... | 07/01/2010 |
| 20100146027 | RESIDUE CALCULATION WITH BUILT-IN CORRECTION IN A FLOATING POINT UNIT A residue generator for calculation and correction of a residue value. The residue generator includes a residue-generation tree connected with an operand register at an input of the residue generator including a plurality of register-bits receiving and carrying bits of ... | 06/10/2010 |
| 20100063987 | SUPPORTING MULTIPLE FORMATS IN A FLOATING POINT PROCESSOR In a binary floating point processor, the exponents of each of the various types of operands are recoded into an internal format, by biasing the exponents with the minimum exponent value of the result precision (“Emin”), i.e., the recoded value of the exponent is th... | 03/11/2010 |
| 20100030833 | APPARATUS, METHOD, AND PROGRAM FOR ARITHMETIC PROCESSING A mantissa/exponent splitter splits an input value X=(1+X1/223)×(2̂X2) into a mantissa X1 and an exponent X2. An interpolation processor references the mantissa/exponent splitter using the mantissa X1 a... | 02/04/2010 |
| 20100023573 | EFFICIENT FORCING OF CORNER CASES IN A FLOATING POINT ROUNDER The forcing of the result or output of a rounder portion of a floating point processor occurs only in a fraction non-increment data path within the rounder and not in the fraction increment data path within the rounder. The fraction forcing is active on a corner case su... | 01/28/2010 |
| 20090300087 | Computation processor, information processor, and computing method A computation processor outputs whether a carry-out is generated, by incrementing a result of computation by 1, during rounding of the result of the computation. The computation processor includes a computing unit that performs the computation; a shift amount calculatin... | 12/03/2009 |
| 20090265409 | PROCESSOR FOR PERFORMING MULTIPLY-ADD OPERATIONS ON PACKED DATA A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor perfo... | 10/22/2009 |
| 20090182795 | Method and system for performing calculations using fixed point microprocessor hardware A method and system are described for performing an arithmetic operation such as multiplication or division of a fixed point variable measured at runtime by a floating point constant known at compile-time. The floating point constant is converted into a mantissa and a b... | 07/16/2009 |
| 20090100121 | APPARATUS AND METHOD FOR LOW COMPLEXITY COMBINATORIAL CODING OF SIGNALS During operation of an encoder, a signal vector (x) is received. A first multi-precision operand (Ψ′k) will be generated based on the signal vector to be encoded. A mantissa operand and an exponent operand are generated. Both the mantissa operand and the e... | 04/16/2009 |
| 20090083358 | EMULATION OF A FIXED POINT OPERATION USING A CORRESPONDING FLOATING POINT OPERATION A computer emulates a fixed-point operation that is normally performed on fixed-point operands, by use of a floating-point operation that is normally performed on floating-point operands. Several embodiments emulate a fixed-point operation by: expanding at least one fix... | 03/26/2009 |
| 20080307030 | GENERATION OF TEST CASES WITH RANGE CONSTRAINTS FOR FLOATING POINT ADD AND SUBTRACT INSTRUCTIONS Methods, apparatus and systems are disclosed for the generation of range-constrained test cases for verification of designs of arithmetic floating point units. Given three ranges of floating point numbers Rx, Ry, Rz, a floating point operation (op), and a rounding-mode ... | 12/11/2008 |
| 20080307028 | GENERATION OF TEST CASES WITH RANGE CONSTRAINTS FOR FLOATING POINT ADD AND SUBTRACT INSTRUCTIONS Methods, apparatus and systems are disclosed for the generation of range-constrained test cases for verification of designs of arithmetic floating point units. Given three ranges of floating point numbers Rx, Ry, Rz, a floating point operation (op), and a rounding-mode ... | 12/11/2008 |
| 20080270496 | COMPOSITION/DECOMPOSITION OF DECIMAL FLOATING POINT DATA A decimal floating point finite number in a decimal floating point format is composed from the number in a different format. A decimal floating point format includes fields to hold information relating to the sign, exponent and significand of the decimal floating point ... | 10/30/2008 |
| 20080270506 | CONVERT SIGNIFICAND OF DECIMAL FLOATING POINT DATA FROM PACKED DECIMAL FORMAT A decimal floating point finite number in a decimal floating point format is composed from the number in a different format. A decimal floating point format includes fields to hold information relating to the sign, exponent and significand of the decimal floating point ... | 10/30/2008 |
| 20080270500 | COMPOSITION OF DECIMAL FLOATING POINT DATA, AND METHODS THEREFOR A decimal floating point finite number in a decimal floating point format is composed from the number in a different format. A decimal floating point format includes fields to hold information relating to the sign, exponent and significand of the decimal floating point ... | 10/30/2008 |
| 20080263120 | METHOD AND SYSTEM FOR OPTIMIZING FLOATING POINT CONVERSION BETWEEN DIFFERENT BASES A method of streamlining floating-point conversions includes determining a source coefficient and a source exponent of an input value represented by a floating-point number in a source base; estimating an approximated target exponent (ATE) using the source coefficient a... | 10/23/2008 |
| 20080155004 | ARITHMETIC CIRCUIT, ARITHMETIC METHOD, AND INFORMATION PROCESSING DEVICE To provide a floating point arithmetic circuit for efficiently defecting an error, which has a large numerical error, with a less circuit amount, the floating point arithmetic circuit comprises a first arithmetic unit for outputting a first arithmetic result, a second a... | 06/26/2008 |
| 20080154999 | Compressed Floating Point Representation Of Points On Monotonic Curves Which Can Be Specified By High Order Equations Using different number of data bits to represent points in corresponding different sections of a high order monotonic curve in a floating point format. More number of data bits are used to represent one section of the curve, while correspondingly fewer data bits are use... | 06/26/2008 |
| 20080046495 | Multi-stage floating-point accumulator A multi-stage floating-point accumulator includes at least two stages and is capable of operating at higher speed. In one design, the floating-point accumulator includes first and second stages. The first stage includes three operand alignment units, two multiplexers, a... | 02/21/2008 |
| 20070266071 | MODE-BASED MULTIPLY-ADD RECODING FOR DENORMAL OPERANDS In a denormal support mode, the normalization circuit of a floating-point adder is used to normalize or denormalized the output of a floating-point multiplier. Each floating-point multiply instruction is speculatively converted to a multiply-add instruction, with the ad... | 11/15/2007 |
| 20070203967 | Floating-point processor with reduced power requirements for selectable subprecision A method and apparatus for performing a floating-point operation with a floating-point processor having a given precision is disclosed. A subprecision for the floating-point operation on one or more floating-point numbers is selected. The selection of the subprecision r... | 08/30/2007 |
| 20070061391 | Floating point normalization and denormalization A data processor includes a first bit field of a first plurality of bits representing a mantissa of a floating point number and a second bit field of a second plurality of bits representing an exponent of the floating point number. The first plurality of bits is partiti... | 03/15/2007 |
| 20070038694 | Method of root operation for voice recognition and mobile terminal thereof A method of a root operation for voice recognition and mobile terminal thereof are disclosed, by which an operational speed faster than that of a Taylor series using method can be provided and by which a memory having a size smaller than that of a table using method is ... | 02/15/2007 |
| 20060184601 | Floating point unit with fused multiply add and method for calculating a result with a floating point unit The invention proposes a Floating Point Unit (1) with fused multiply add, with one addend operand (eb, fb) and two multiplicand operands (ea, fa; ec, fc), with a shift amount logic (2) which based on the exponents of the operands (ea, eb and ec) computes a... | 08/17/2006 |
| 20060179098 | System and method for reduction of leading zero detect for decimal floating point numbers A method for leading zero detection. The method includes receiving DPD encoded data representing a three digit BCD number and determining directly from the DPD encoded data if the BCD number represented by the DPD encoded data contains at least one leading zero digit. A... | 08/10/2006 |
| 20060179099 | System and method for performing decimal floating point addition A method for performing a decimal floating point operation. A first operand including a first coefficient and a first exponent is received. The method also includes receiving a second operand that includes a second coefficient and a second exponent. An operation associa... | 08/10/2006 |
| 20060179097 | System and method for a floating point unit with feedback prior to normalization and rounding A system for performing floating point arithmetic operations including an input register adapted for receiving an operand. The system also includes a mechanism for performing a shift or masking operation in response to determining that the operand is in an un-normalized... | 08/10/2006 |
| 20060161612 | Method and structure for a generalized cache-register file interface with data restructuring methods for multiple cache levels and hardware pre-fetching A method and structure for executing a matrix algorithm requiring an order of N3 operations including data reformatting operations, where N is a dimension of an operand of said algorithm on a computer, includes initially reformatting data for at least one mat... | 07/20/2006 |
| 20060136540 | Enhanced fused multiply-add operation An apparatus, method, and system for performing an enhanced fused multiply-add operation is disclosed. In one embodiment, an apparatus includes an exponent unit. The exponent unit includes a first adder to generate S1, where S1 is the sum of an integer k, ... | 06/22/2006 |
| 20060112160 | Floating-point number arithmetic circuit Disclosed herein is a floating-point number arithmetic circuit for efficiently supplying data to be performed arithmetic operation. The floating-point number arithmetic circuit includes an floating-point number arithmetic unit for performing a predetermined floating-poi... | 05/25/2006 |
| 20060106909 | System and method for mapping mathematical finite floating-point numbers A floating-point number is encoded into a binary string. A left-to-right comparison of the binary string determines relative magnitude of the floating-point number. If the floating-point number is negative, then take an absolute value of the floating-point number. The r... | 05/18/2006 |
| 20060053190 | Construction of a folded leading zero anticipator An apparatus, a method, and a computer program are provided for anticipating leading zeros for a Floating Point (FP) computation. Traditional leading zero anticipators (LZA) are typically very wide. To reduce the width of the LZA, it is subdivided to two smaller LZA tha... | 03/09/2006 |
| 20060053191 | Floating point encoding systems and methods Systems and methods for encoding floating point numbers. A system can include encoding logic which encodes invalid floating point representations as valid data. Decoding logic can be used to recognize the invalid floating point representations and map can provide the in... | 03/09/2006 |
| 20060047739 | Decimal floating-point adder A decimal floating-point adder is described that performs addition and subtraction on decimal floating-point operands. The decimal floating-point adder includes an alignment unit that receives a first floating-point number and a second floating-point number, and aligns ... | 03/02/2006 |
