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| Application No. | Application Title | Issue Date |
| 20110231467 | MONTGOMERY MULTIPLIER HAVING EFFICIENT HARDWARE STRUCTURE A radix-2k Montgomery multiplier including an input coefficient generation unit to receive a multiplier, a multiplicand, a modulus, a sum and a previous sum, to generate and to output a partial product and a multiple modulus by using at least one of the multiplier, the ... | 09/22/2011 |
| 20100325186 | Processing with Compact Arithmetic Processing Element A processor or other device, such as a programmable and/or massively parallel processor or other device, includes processing elements designed to perform arithmetic operations (possibly but not necessarily including, for example, one or more of addition, multiplication,... | 12/23/2010 |
| 20100281092 | STANDARD CELL FOR ARITHMETIC LOGIC UNIT AND CHIP CARD CONTROLLER A masked ALU cell for a certain bit position p is provided. The cell comprises a base unit operable to generate a masked inverted carry out bit co*_n and an inverted masked sum bit s*_n based on a first masked output a*, a second masked output b*, and a re-masked carry ... | 11/04/2010 |
| 20100191793 | Symbolic Computation Using Tree-Structured Mathematical Expressions A method for performing symbolic computations on a mathematical expression. The mathematical expression may be converted to a tree structure having one or more parent nodes and one or more child nodes. Each parent node may be a mathematical operation. Each child node ma... | 07/29/2010 |
| 20100007379 | PROGRAMMABLE LOGIC DEVICES WITH FUNCTION-SPECIFIC BLOCKS A programmable logic integrated circuit device has at least one function-specific circuit block (e.g., a parallel multiplier, a parallel barrel shifter, a parallel arithmetic logic unit, etc.) in addition to the usual multiple regions of programmable logic and the usual... | 01/14/2010 |
| 20090265410 | Packed add-subtract operation in a microprocessor A packed half-word addition and subtraction operation is performed by a microprocessor in parallel upon half-word operands obtained from designated top or bottom half-word locations of designated source registers of a register file and the sum and difference results of ... | 10/22/2009 |
| 20090248772 | Single-Level Parallel-Gated Carry/Majority Circuits And Systems Therefrom A carry/majority circuit, comprising a plurality of differential transistor pairs coupled in parallel and forming a pair of output nodes, with a single parallel gated level. Current is steered through a leg of the transistor pair having a higher input voltage.... | 10/01/2009 |
| 20080281896 | INDUSTRIAL CONTROLLER A first arithmetic operator (11) includes a first modular arithmetic coding encoder (11b) for encoding a numeric data transmitted by a command from a central controller (31) into a modular arithmetic code, a first arithmetic operation process... | 11/13/2008 |
| 20080154996 | DATAPIPE SYNCHRONIZATION DEVICE A programmable element for data processing comprises a crosspoint switch (318), a mathematical operation module (320), and a plurality of data hold modules (604,606). Each of the data hold modules (604,606) receives data from the crosspoint s... | 06/26/2008 |
| 20080147767 | BINOMIAL OPTIONS PRICING MODEL COMPUTATIONS USING A PARALLEL PROCESSOR Binomial options pricing model computations are performed on node values of a lattice using a parallel processor such as a single-instruction, multiple-data processor. The parallel processor stores computational data in on-chip memory. Data to be processed by a group of... | 06/19/2008 |
| 20080140750 | Apparatus and method for performing rearrangement and arithmetic operations on data An apparatus and method are provided for performing rearrangement operations and arithmetic operations on data. The data processing apparatus has processing circuitry for performing SIMD processing operations and scalar processing operations, a register bank for storing... | 06/12/2008 |
| 20080140749 | Method and device for performing a quantum algorithm to simulate a genetic algorithm A method and device for performing a quantum algorithm where the superposition, entanglement with interference operators determined for performing selection, crossover, and mutation operations based upon a genetic algorithm. Moreover, entanglement vectors generated by t... | 06/12/2008 |
| 20080126747 | METHODS AND APPARATUS TO IMPLEMENT HIGH-PERFORMANCE COMPUTING Apparatus and methods to implement high-performance computing are disclosed. An example method comprises executing a first operating system in a first partition to detect an arithmetic instruction, using an inter-partition bridge to notify a second partition of the arit... | 05/29/2008 |
| 20080126465 | Calendar-based Financial Calculator A computer operated, calendar-based financial calculator comprises a computer display, calendar calculating software, and a calculation engine, so as to provide a visual presentation of any calendar month. Each day of each month of each year has a unique numerical value... | 05/29/2008 |
| 20080114825 | DIGITAL SIGNAL PROCESSING APPARATUS AND DIGITAL SIGNAL PROCESSING METHOD A digital signal processing apparatus including: an arithmetic circuit that performs first digital signal processing on an input signal SA sampled at a first sampling frequency f1 and second digital signal processing on a result of the first digital signal proces... | 05/15/2008 |
| 20080114824 | Single Precision Vector Permute Immediate with "Word" Vector Write Mask The present invention is generally related to the field of image processing, and more specifically to an instruction set for processing images. Vector processing may involve performing a plurality of permute operations to arrange vector operands in desired locations of ... | 05/15/2008 |
| 20080091757 | System and method for web enabled geo-analytics and image processing A method for providing mapping, data management and analysis. Creation of a map is initiated with a desired Gaussian aggregation and desired color map parameters. Data is loaded to be utilized in the map. The data is rasterized, then converted to a certain scale. A conv... | 04/17/2008 |
| 20080059551 | Device and Method for Composing Codes Configurable vector processors can be equipped with code generators, so that they are capable of handling different standards and codes. Furthermore, they can be arranged to provide support for related functions such as cyclic redundancy check (CRC). A configurable vect... | 03/06/2008 |
| 20080040414 | Standard cell for arithmetic logic unit and chip card controller A cell for an arithmetic logic unit includes a first input; a second input; a carry-in input; a first control input and a second control input; and a circuit connected to the first input, the second input, the carry-in input, the first control input, and the second cont... | 02/14/2008 |
| 20070299898 | SYSTEM AND METHOD FOR IMPLEMENTING IRREGULAR DATA FORMATS A computer system comprises a processing unit configured to process fixed size data words comprising at least one exponent field of variable size and a mantissa of variable size; an input device configured to provide data words to the processing unit; and an output devi... | 12/27/2007 |
| 20070276895 | Low-voltage CMOS circuits for analog decoders Low-voltage CMOS (Complementary Metal Oxide Semiconductor) circuits, suitable for analog decoders, for example, are provided. The circuits include multiplier modules that receive first input signals and respective ones of a plurality of second input signals. Each multip... | 11/29/2007 |
| 20070260664 | Computation of a multiplication operation with an electronic circuit and method A computing method and circuit for computing a modular operation with at least one operand having a binary representation. Iteratively for each bit of this operand, doubling the value of an intermediate result stored in a first memory element by shifting the bits of the... | 11/08/2007 |
| 20070260662 | Controlled-Precision Iterative Arithmetic Logic Unit A controlled-precision Iterative Arithmetic Logic Unit (IALU) included in a processor produces sub-precision results, i.e. results having a bit precision less than full precision. In one embodiment, the controlled-precision IALU comprises an arithmetic logic circuit and... | 11/08/2007 |
| 20070260663 | Cyclic segmented prefix circuits for mesh networks Parallel prefix circuits for computing a cyclic segmented prefix operation with a mesh topology are disclosed. In one embodiment of the present invention, the elements (prefix nodes) of the mesh are arranged in row-major order. Values are accumulated toward the center o... | 11/08/2007 |
| 20070250559 | Broadband transfer function synthesis using orthonormal rational bases In order to generate a broadband transfer function of complex characteristics of a linear time-invariant (LTI) system, data characterising properties of the system are acquired. A set of poles in the complex plane are defined to characterise the system, and then an iter... | 10/25/2007 |
| 20070239817 | Rounding computing method and computing device therefor A computing device has a rounding processor that inputs therein a set of plural (K) input data IN1 through INK comprising z bits. The rounding processor selects an ensured bit field depending upon the state of usage of each of specific areas A of upper z/2 bits o... | 10/11/2007 |
| 20070239816 | Formation Process for Logical and Control Functions in Information Processing and Control Systems The invention concerns generally radio electronics in particular it relates to computer facilities and can be used in information processing and control systems. The process includes an operation of input of two data to be compared; the first operation of addition of in... | 10/11/2007 |
| 20070233767 | Rotator/shifter arrangement Embodiments related to rotator/shifter arrangements are presented herein. ... | 10/04/2007 |
| 20070233766 | SYSTEM AND METHOD FOR COMPILING SCALAR CODE FOR A SINGLE INSTRUCTION MULTIPLE DATA (SIMD) EXECUTION ENGINE A system, method, and computer program product are provided for performing scalar operations using a SIMD data parallel execution unit. With the mechanisms of the illustrative embodiments, scalar operations in application code are identified that may be executed using v... | 10/04/2007 |
| 20070233768 | Method and circuit arrangement for computing a value of a complex signal The invention relates to continuous computing of an averaged value of a complex signal, in which values are produced by iterative processing, such as CORDIC processing, from digital complex input values of in-phase and quadrature components (si, sq) of the complex signa... | 10/04/2007 |
| 20070226287 | MIMO RECEIVER AND METHOD FOR BEAMFORMING USING CORDIC OPERATIONS Embodiments of a MIMO receiver and method for beamforming using CORDIC operations are generally described herein. Other embodiments may be described and claimed. In some embodiments, complex singular value decomposition (SVD) operations are performed on a channel matrix... | 09/27/2007 |
| 20070214204 | Negative two's complement numbering system The present invention provides a solution to the shortcomings of the traditional two's complement system that is commonly utilized in modern computing systems and digital signal processors. The previously described shortcoming of the two's... | 09/13/2007 |
| 20070198625 | Conditional negating booth multiplier An angle rotator performs angle rotation of an input complex signal in the complex plane according to an angle θ. The angle rotator includes a coarse stage rotation and a fine stage rotation. The two specific amounts of rotation are obtained directly from the original ... | 08/23/2007 |
| 20070198624 | Using a Document Model to Create and Maintain Dynamic Mathematic Representations Through Problem Spaces A device operable to maintain a document comprising a processor, a first problem space including a first variable having a first value, and a second problem space including a second variable having a second value, the first and second variables and the first and second ... | 08/23/2007 |
| 20070192395 | METHOD FOR DATABASE-DRIVEN ESTIMATE OF AN OUTPUT QUANTITY IN A K-DIMENSIONAL VALUE RANGE Method for the database-driven estimate of an output quantity in a k-dimensional value range. The method includes determining a location probability range Ri for a k-dimensional output quantity for an element i of a measurement series {i=1, . . . ,n}, in whic... | 08/16/2007 |
| 20070174378 | Computation of logarithmic and exponential functions Efficiency of computation of logarithmic and exponential functions may be improved using multiplication by pre-computed coefficients to obtain intermediate products. ... | 07/26/2007 |
| 20070168410 | TRANSFORMS WITH COMMON FACTORS Techniques for efficiently performing transforms on data are described. In one design, an apparatus performs multiplication of a first group of at least one data value with a first group of at least one rational dyadic constant that approximates a first group of at leas... | 07/19/2007 |
| 20070156802 | Method and apparatus for initializing interval computations through subdomain sampling One embodiment of the present invention provides a system that uses a computer to evaluate a function within a domain using an interval computing technique. During operation, the system receives the function and the domain over which the function is to be evaluated. Nex... | 07/05/2007 |
| 20070136411 | Cyclic redundancy checking value calculator A CRC value calculator enables throughput to be improved while keeping down the increase in the size of the circuitry. This is achieved by using (n+1) basic CRC circuits to configure a CRC value calculator in which the width of the data processed during one clock cycle ... | 06/14/2007 |
| 20070094320 | Parallel Adder-Based DCT / IDCT Design Using Cyclic Convolution A device and method are described that apply 1-D and 2-D discrete cosine transforms (DCT) and inverse discrete cosine transforms (IDCT) to sets of input data, typically 8×8 or 16×16 matricies of coefficients. One device includes input lines, logic to pre-add input val... | 04/26/2007 |
