Class 703/19 - Timing

Subclass of Class 703 - Data processing: structural design, modeling, simulation, and emulation
Definition: Subject matter wherein the timing delay of the electrical
No. of applications: 68
Last issue date: 11/24/2011

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Application No.	Application Title	Issue Date
20110288847	PREDICTING DATABASE SYSTEM PERFORMANCE A prediction system may perform capacity planning for one or more resources of a database systems, such as by understanding how different workloads are using the system resources and/or predicting how the performance of the workloads will change when the hardware config...	11/24/2011
20110282641	METHOD AND SYSTEM FOR REAL-TIME PARTICLE SIMULATION A method and system for particle simulation are provided in which the number of particles is held as close as possible below a prescribed particle limit. When adding new particles to the simulation results in approaches the particle limit, new particles which contribute...	11/17/2011
20110276321	DEVICE SPECIFIC CONFIGURATION OF OPERATING VOLTAGE A method and circuit for device specific configuration of an operating voltage is provided. A circuit design is analyzed to determine a maximum gate-level delay for the circuit design. A minimum voltage value corresponding to the maximum gate-level delay is determined a...	11/10/2011
20110224965	Modeling Loading Effects of a Transistor Network A system, method and program product for modeling load effects of a load CCC (channel connected component) in a transistor network. A system is disclosed that includes an analysis system that determines allowable logical state and transition functions for nets in a load...	09/15/2011
20110046937	DELAY ANALYSIS PROCESSING OF SEMICONDUCTOR INTEGRATED CIRCUIT A delay analysis device composed of a storage device and a data processing device analyzes a chip fabricating a semiconductor integrated circuit. Delay calculation is performed via an RC simulation with reference to a layout-implemented macro net list, macro layout data...	02/24/2011
20110015916	SIMULATION METHOD, SYSTEM AND PROGRAM A simulation system having multiple peripherals that communicate with each other. The system includes a weighted graph with weights set as communication times. The peripherals are represented as nodes and connection paths are represented as edges. Among the communicatio...	01/20/2011
20110004456	VIRTUAL NETWORK EMBEDDING METHOD IN WIRELESS TEST-BED NETWORK Provided is a technology for providing an efficient embedding method in virtualizing a wireless test-bed network. In a virtual network embedding method in a wireless test-bed network, at least one packing point is generated in a two-dimensional strip comprised of time a...	01/06/2011
20100235158	Automated System Latency Detection for Fabric Simulation A configuration manager identifies a first device and a second device within a simulated system. Each device within the simulated system includes an inbound port and an outbound port. Next, the configuration manager injects a simulation only packet, at an “outbound ti...	09/16/2010
20100153897	SYSTEM AND METHOD FOR EMPLOYING SIGNOFF-QUALITY TIMING ANALYSIS INFORMATION CONCURRENTLY IN MULTIPLE SCENARIOS TO REDUCE LEAKAGE POWER IN AN ELECTRONIC CIRCUIT AND ELECTRONIC DESIGN AUTOMATION TOOL INCORPORATING THE SAME A leakage power recovery system and method, and a electronic design automation (EDA) tool incorporating either or both of the system and the method. In one embodiment, the timing signoff tool includes: (1) a power recovery module configured to carry out an instance of a...	06/17/2010
20100057429	METHOD AND APPARATUS FOR PARALLELIZATION OF SEQUENTIAL POWER SIMULATION One particular implementation takes the form of an apparatus or method for parallelizing a sequential power simulation of an integrated circuit device. The implementation may temporally divide the simulation so that separate time segments of the simulation can be run at...	03/04/2010
20100050144	SYSTEM AND METHOD FOR EMPLOYING SIGNOFF-QUALITY TIMING ANALYSIS INFORMATION TO REDUCE LEAKAGE POWER IN AN ELECTRONIC CIRCUIT AND ELECTRONIC DESIGN AUTOMATION TOOL INCORPORATING THE SAME A leakage power recovery system and method, and a electronic design automation (EDA) tool incorporating either or both of the system and the method. In one embodiment, the timing signoff tool includes: (1) a power recovery module configured to make first conditional rep...	02/25/2010
20090319254	CHARGE-BASED MILLER COEFFICIENT COMPUTATION A method of estimating a Miller coefficient for an aggressor network and a victim network coupled by a coupling capacitor includes synthesizing a reduced order system from the aggressor network and the victim network, estimating an active area across the coupling capaci...	12/24/2009
20080319730	Method and Apparatus for Modifying a Virtual Processor Model for Hardware/Software Simulation A method of transforming a provided virtual processor model to a user virtual processor model. Also a tool, e.g., provided as instructions for operating in a host computer system for converting a provided virtual processor model to a user virtual processor model. Also a...	12/25/2008
20080294415	TROUBLESHOOTING TEMPORAL BEHAVIOR IN "COMBINATIONAL" CIRCUITS A method and computer product is provided to generate a signal model for use in analyzing a model system including imposing an explicit time assumption for each time instant of the system model. The time assumptions are defined so that any two assumptions contradict eac...	11/27/2008
20080294416	FACILITATING SIMULATION OF A MODEL WITHIN A DISTRIBUTED ENVIRONMENT Simulation of models within a distributed environment is facilitated. A model is partitioned based on clock domains, and communication between partitions on different processors is performed on synchronous clock boundaries. Further, data is exchanged across the network ...	11/27/2008
20080216035	METHOD AND COMPUTER PROGRAM FOR CONFIGURING AN INTEGRATED CIRCUIT DESIGN FOR STATIC TIMING ANALYSIS A method and a computer program for configuring an integrated circuit design for static timing analysis include receiving module data representative of a hierarchy of modules in an integrated circuit design. A configuration item is selected from a list of configuration ...	09/04/2008
20080154571	Timing analysis method and apparatus for enhancing accuracy of timing analysis and improving work efficiency thereof A timing analysis apparatus has a block simulation information storing section, a SPICE deck generating section, and a feedback-based static timing analyzing section. The block simulation information storing section stores simulation information for each block when perf...	06/26/2008
20080141201	BLACK BOX TIMING MODELING METHOD AND COMPUTER SYSTEM FOR LATCH-BASED SUBSYSTEM Provided is a black box timing modeling method for a digital circuit comprising synchronous elements including latches. The method includes: characterizing a setup time arc by extracting a setup time with respect to a rising or falling edge of a clock of a synchronous e...	06/12/2008
20080072197	System and Method for Asynchronous Clock Modeling in an Integrated Circuit Simulation A system and method for asynchronous clock modeling in an integrated circuit simulation are provided. The mechanisms of the illustrative embodiments provide clock skewing logic for phase shifting a clock signal in an integrated circuit design. This clock skewing logic a...	03/20/2008
20080052651	Methods to generate state space models by closed forms for general interconnect and transmission lines, trees and nets, and their model reduction and simulations There is provided a set of methods for generating state space models of general VLSI interconnect and transmission lines, trees and nets by closed forms with exact accuracy and low computation complexity. The state space model is built by three types of models: the bran...	02/28/2008
20070288220	Method and Device for Simulating an Automation System A method and a device for simulating an automation system are disclosed. The aim of the invention is to allow an automation system to be simulated in such a way that simulation components operating at very different computing speeds can be combined into an overall simul...	12/13/2007
20070288221	TIMING CONTROL METHOD OF HARDWARE-SIMULATING PROGRAM AND APPLICATION OF THE SAME A timing-control method of a hardware-simulating program can be applied to a software platform for facilitating control program development. The hardware-simulating program can be recorded in any suitable recording medium and defines therein a plurality of simulating el...	12/13/2007
20070249918	SIGNAL PROCESSING APPARATUS The present disclosure describes a method and an apparatus for analyzing measured signals using various processing techniques. In certain embodiments, the measured signals are physiological signals. In certain embodiments, the measurements relate to blood constituent me...	10/25/2007
20070244686	Calibration method for mixed-mode simulation A calibration method of a mixed mode simulation calibrates standard delay times in a standard delay format and includes obtaining a digital output circuit from a digital circuit, obtaining an analog output circuit from an analog circuit, performing a simulation on the d...	10/18/2007
20070225960	SUBCHIP BOUNDARY CONSTRAINTS FOR CIRCUIT LAYOUT An electric circuit is laid out through a process comprising estimating signal propagation time in an interface between a source and a destination subcircuit, calculating a margin time based on the difference between a clock period and the estimated signal propagation t...	09/27/2007
20070208552	Analyzing Timing Uncertainty in Mesh-Based Architectures A method of analyzing timing uncertainty involves creating an accurate model of one or more circuit elements of a mesh circuit residing within a window that covers a subset of the mesh circuit. An approximate model of one or more circuit elements of the mesh circuit res...	09/06/2007
20070203683	Timing Wires in a Graphical Program A system and method for specifying timing relationships among nodes in a graphical program. User input specifying desired timing of a first node with respect to timing of a second node may be received. In various embodiments, any kind of timing relationship or timing co...	08/30/2007
20070192079	Run-time switching for simulation with dynamic run-time accuracy adjustment Systems and methods for run-time switching for simulation with dynamic run-time accuracy adjustment. In one embodiment, a computer implemented method performs a simulation of a computer instruction executing on a simulated hardware design by a first simulation model, wh...	08/16/2007
20070055487	Forming statistical model of independently variable parameters for timing analysis Forming of a statistical model for a set of independently variable parameters for analysis of a circuit design is disclosed. In one embodiment, a method includes establishing a timing model including delay and delay changes due to process parameter variations (Pi) that ...	03/08/2007
20070016882	Sliding Window Scheme (SWS) for Determining Clock Timing in a Mesh-Based Clock Architecture In one embodiment, a method includes accessing a description of a chip including multiple sequential elements and a clock mesh, information for modeling the sequential elements and interconnections, and a set of parameters of the clock mesh. The method also includes, us...	01/18/2007
20070016394	System and method for using model analysis to generate directed test vectors A mechanism for exploiting the data gathered about a system model during the system design phase to aid the identification of errors subsequently detected in a deployed system based on the system model is disclosed. The present invention utilizes the coverage analysis f...	01/18/2007
20070005329	Building integrated circuits using a common database Systems and methods for designing and generating integrated circuits using a high-level language are described. The high-level language is used to generate performance models, functional models, synthesizable register transfer level code defining the integrated circuit,...	01/04/2007
20060282251	Method, apparatus, and computer program product for facilitating modeling of a combinatorial logic glitch at an asynchronous clock domain crossing A method, apparatus and computer program product are provided for facilitating combinatorial logic modeling at an asynchronous clock domain crossing. The modeling technique employs a simulation value of X in combinatorial logic at the asynchronous clock domain crossing ...	12/14/2006
20060206845	Hybrid linear wire model approach to tuning transistor widths of circuits with RC interconnect A hybrid linear wire model for tuning the transistor widths of circuits linked by RC interconnects is described. The method uses two embedded simulators during the tuning process on netlists that contain resistors (Rs). A Timing oriented simulator is used only for timin...	09/14/2006
20060195310	Efficient clock models and their use in simulation Methods simulating a system of devices are described. A model that simulates the system is executed. The system model includes a plurality of modules. A clock object for a module can be disabled when it is not needed or not being used. ...	08/31/2006
20060190235	Verilog HDL simulation model for retain time A computer program product for making a machine simulating the behavior of retain and access time of output bus is presented. The computer program product can make a simulator for detecting the transition of an input/bidirectional pin. In the retain time of the related ...	08/24/2006
20060155523	Method and device for representing a cell implemented in a partially depleted silison-on-insulator type CMOS technology A first simulation running through all the possible input states is used to collect information on the drain, gate and source biasing of each transistor. This transistor bias information is used to perform an interpolation in charts of internal potentials. These charts ...	07/13/2006
20060111885	Method of circuit simulation for delay characteristic evaluation, circuit simulation program and circuit simulation device In delay characteristic evaluation of a logical circuit, there was the problem of underestimation of the output load compared with the actual output load. There is provided a simulation device including a simplification section that, simplifies the load circuit using a ...	05/25/2006
20060090149	SIMULATION TESTING OF DIGITAL LOGIC CIRCUIT DESIGNS A method and system for testing a circuit design. The method including generating a simulation model of the circuit design, the circuit design comprising one or more source latches, one or more destination latches and a logic function connected between the source latche...	04/27/2006
20060069539	Method of generating simulation model For the purpose of providing a simulation model allowing gate simulation but is capable of keeping the circuit information on the functional block (IP) secret, a method of generating a simulation model provided herein by the present invention comprises a step of generat...	03/30/2006

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Class 703/19 - Timing