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| Application No. | Application Title | Issue Date |
| 20120053924 | SYSTEM AND METHOD FOR EXECUTING FUNCTIONAL SCANNING IN AN INTEGRATED CIRCUIT ENVIRONMENT An example method is provided and includes executing a functional test for an integrated circuit and observing a failure associated with the integrated circuit. The method also includes executing a functional scan mode in order to reproduce the failure associated with t... | 03/01/2012 |
| 20120046931 | MULTIPLE POWER-SUPPLY SIMULATION RESULT ANALYZER AND METHOD OF ANALYZING THE SAME In a method of displaying a waveform of a simulation result, a waveform file extractor which extracts information of voltage values in addition to simulation times, values, and signal names input as waveform information, and a waveform display unit which enables a displ... | 02/23/2012 |
| 20110295584 | VERIFICATION SUPPORT PROGRAM, LOGIC VERIFICATION DEVICE, AND VERIFICATION SUPPORT METHOD A computer-readable recording medium configured to store a verification support program, the program causing a computer to execute logic verification operations for a system including a plurality of control circuits, and a plurality of hardware units that correspond to ... | 12/01/2011 |
| 20110270599 | METHOD FOR TESTING INTEGRATED CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE A method for testing an integrated circuit includes simulating the integrated circuit and generating waveforms of signals at a plurality of nodes of the integrated circuit, generating a text file representing the signal waveforms by detecting a waveform change of the si... | 11/03/2011 |
| 20110257955 | Gate-Level Logic Simulator Using Multiple Processor Architectures Techniques for simulating operation of a connectivity level description of an integrated circuit design are provided, for example, to simulate logic elements expressed through a netlist description. The techniques utilize a host processor selectively partitioning and op... | 10/20/2011 |
| 20110238400 | DEVICE FOR A METHOD OF MODELLING A PHYSICAL STRUCTURE A device (100) for modelling a physical structure by a number of finite state machines comprising a simulation unit (114) adapted for simulating the physical structure by a number of finite state machines, a recording unit (104) adapted for recordin... | 09/29/2011 |
| 20110213605 | Satisfiability (SAT) Based Bounded Model Checkers Systems and methods that use a solver to find bugs in a target model of a computing system having one or more finite computation paths are provided. The bugs on computation paths of less than a predetermined length are detected by translating the target model to include... | 09/01/2011 |
| 20110161066 | DELTA RETIMING IN LOGIC SIMULATION Aspects of the present invention are directed to improving the speed of event-driven simulation by manipulating delta delays in a system model to reduce delta cycle executions. The manipulation is performed in a manner that preserves delta cycle accurate timing on selec... | 06/30/2011 |
| 20110054876 | PHYSICAL REALIZATIONS OF A UNIVERSAL ADIABATIC QUANTUM COMPUTER Devices, methods and articles advantageously allow communications between qubits to provide an architecture for universal adiabatic quantum computation. The architecture includes a first coupled basis A1B1 and a second coupled basis A2B<... | 03/03/2011 |
| 20100324881 | SATISFIABILITY (SAT) BASED BOUNDED MODEL CHECKERS A method uses a SAT solver operating to cycle k to find bugs in a model having finite computation paths therein, wherein said bugs are on computation paths of less than length k. Another method includes adding an additional state variable to a model to be checked, where... | 12/23/2010 |
| 20100318952 | System and Method Incorporating An Arithmetic Logic Unit For Emulation A system and method for verifying logic circuit designs having arithmetic operations and complex logical operations such that the operations may be evaluated at substantially full hardware speed is disclosed. According to one embodiment, a system for verifying the funct... | 12/16/2010 |
| 20100318328 | DESIGN SUPPORT SYSTEM AND METHOD FOR MANUFACTURING INTEGRATED CIRCUIT To efficiently manufacture an integrated circuit including an I/O register. On the basis of behavior level design data 851, I/O register access information 852 is generated which includes information on access control from a user logical circuit 313... | 12/16/2010 |
| 20100305934 | LOGICAL SIMULATION SYSTEM, LOGICAL SIMULATION METHOD, AND LOGICAL SIMULATION PROGRAM A program that simulates a netlist data including a plurality of basic elements using a computer includes a logic operation section configured to stipulate a logic operation of at least one of the plurality of the basic elements, a change detection section configured to... | 12/02/2010 |
| 20100305933 | Method and Apparatus for Verifying Logic Circuits Using Vector Emulation with Vector Substitution A method for verifying a logic circuit in a prototyping system includes (a) configuring programmable logic circuits of the prototyping system to implement the logic circuit and to implement probe circuits for accessing internal nodes of the logic circuit; (b) preparing ... | 12/02/2010 |
| 20100286976 | Systems and Methods for Logic Verification Methods and systems for simulating logic may translate logic design into executable code for a multi-processor based parallel logic simulation device. A system may implement one or more parallel execution methods, which may include IPMD, MPMD, and/or DDMT.... | 11/11/2010 |
| 20100174521 | DATA PROCESSING WITH CIRCUIT MODELING Various aspects of the present invention are directed to design modeling and/or processing of streaming data. According to an example embodiment, a system to model a hardware specification includes a platform (106) arranged to receive an input data stream and tra... | 07/08/2010 |
| 20100146338 | AUTOMATED SEMICONDUCTOR DESIGN FLAW DETECTION SYSTEM The process by which a logical simulation model is implemented in a physical device may introduce errors in the resulting implementation. A simulation system enables comparison of a realized physical implementation against the simulation models that produce them, thereb... | 06/10/2010 |
| 20100138710 | LOGIC VERIFICATION APPARATUS To provide a logic verification apparatus capable of preventing, when an indeterminate value is generated in logic verification, the indeterminate value from being unintentionally erased. A simulation part performs a simulation based on a d... | 06/03/2010 |
| 20100106477 | MEDIUM STORING LOGIC SIMULATION PROGRAM, LOGIC SIMULATION APPARATUS, AND LOGIC SIMULATION METHOD A logic simulation apparatus includes: a jitter detector generation section 21 that generates information concerning a jitter circuit for determining whether a time variation occurs in signal passing between a first circuit and a second circuit, the first circuit... | 04/29/2010 |
| 20100102825 | Spectral and information theoretic method of test point, partial-scan, and full-scan flip-flop insertion to improve integrated circuit testability Design for testability (DFT) algorithms, which use both gradient descent and linear programming (LP) algorithms to insert test points (TPs) and/or scanned flip-flops (SFFs) into large circuits to make them testable are described. Scanning of either all flip-flops or a s... | 04/29/2010 |
| 20100094610 | Circuit simulation model generation apparatus, circuit simulation model generation method and circuit simulation apparatus A circuit simulation model generation apparatus includes: a power supply wiring model generation section that generates a power supply wiring model which is a model of the power supply wiring; a logic circuit model generation section that generates a logic circuit model... | 04/15/2010 |
| 20100076742 | SIMULATION MODEL FOR TRANSISTORS Various embodiments include methods and apparatus for simulating a transistor using a simulation model that includes a transistor simulation model coupled to diode simulation model.... | 03/25/2010 |
| 20100017187 | RANDOM INITIALIZATION OF LATCHES IN AN INTEGRATED CIRCUIT DESIGN FOR SIMULATION Latches in a net of a simulated integrated circuit design are initialized to known logical states prior to application of a reset signal at the beginning of the simulation. The logical states may be set by generating a list of the latches, sorting them in random order, ... | 01/21/2010 |
| 20100004904 | DISPLAY DESIGNING SYSTEM AND METHOD FOR DESIGNING A DISPLAY A display designing system and a method thereof. The display designing system includes a variety of operation modules and an integration module. After receiving initial parameters and selecting operation type parameters, the operation modules generate operation results ... | 01/07/2010 |
| 20090313001 | SIMULATION APPARATUS, SIMULATION METHOD AND COMPUTER-READABLE RECORDING MEDIUM ON OR IN WHICH SIMULATION PROGRAM IS RECORDED The present invention relates to a technique for executing performance evaluation simulation of a system to be implemented by software or hardware. A simulation apparatus includes a first acquisition section for executing existing tentative software to acquire a first e... | 12/17/2009 |
| 20090300558 | USE OF STATE NODES FOR EFFICIENT SIMULATION OF LARGE DIGITAL CIRCUITS AT THE TRANSISTOR LEVEL A method is provided for simulating a sequential digital circuit module given a set of input conditions and a current state for the circuit. The method comprises initiating all state nodes of the circuit module to logic values stored in the current state, initializing a... | 12/03/2009 |
| 20090259453 | Method of modeling SRAM cell A method of modeling an SRAM cell is provided. Initially, transistor models are provided based on transistor devices, and an SRAM cell model is provided including the transistor models. The present methodology streamlines the modeling process by modeling in order the pu... | 10/15/2009 |
| 20090254331 | COMPACT CIRCUIT-SIMULATION OUTPUT Embodiments of a computer system for simulating a circuit are described. During a first mode of the simulation, the computer system stores primary signals and circuit relationships between primary signals and secondary signals associated with a portion of the circuit in... | 10/08/2009 |
| 20090248386 | DESCRIPTION PROCESSING DEVICE, DESCRIPTION PROCESSING METHOD, AND RECORDING MEDIUM A description processing device has: a receiving unit which receives a behavior level description; a label-name generating unit which generates a label name; a label disposing unit which disposes a top label statement; an extracting unit which extracts an extracted labe... | 10/01/2009 |
| 20090240483 | SYSTEM AND COMPUTER PROGRAM PRODUCT FOR AUTOMATIC LOGIC MODEL BUILD PROCESS WITH AUTONOMOUS QUALITY CHECKING A computer program product stored including machine executable instructions stored on machine readable media, the instructions configured for performing automatic logic build processes and implementing autonomic quality checking, by implementing a method including: prov... | 09/24/2009 |
| 20090222252 | DATA DRIVEN LOGIC SIMULATION CHIP AND TOOLCHAIN An apparatus and method may be used for compiling a hardware logic design into data-driven logic programs to be executed on a data-driven chip. The apparatus may include storage with a library for defining a net-list synthesized by a synthesis tool. The apparatus may al... | 09/03/2009 |
| 20090182545 | Simulating an Operation of a Digital Circuit A method for simulating an operation of a digital circuit (01) is described. The method utilizes cycle simulation, wherein in a cycle based simulation model (34) of the digital circuit (01) components (02, 03, 04, 05) of the digital circuit (... | 07/16/2009 |
| 20090171645 | LOGIC SIMULATOR AND LOGIC SIMULATION METHOD According to one embodiment, a logical circuit to be simulated includes a timing network and a specific logical device. The timing network transmits a logical value change of an input signal in correspondence with an elapse of time or clock number increments. The specif... | 07/02/2009 |
| 20090164197 | METHOD FOR TRANSFORMING OVERLAPPING PATHS IN A LOGICAL MODEL TO THEIR PHYSICAL EQUIVALENT BASED ON TRANSFORMATION RULES AND LIMITED TRACEABILITY A method for transforming paths in a logical model to their physical equivalent in a physical model is provided. A logical model is retrieved. All entities in the logical model are mapped. All paths connecting the entities of the logical model are mapped. Tables are cre... | 06/25/2009 |
| 20090144044 | Logic simulator and logic simulation method A logic simulator includes a storage device and a simulator part. The storage device stores a signal duration delay file which associates first signal duration information indicating duration of an input signal supplied to a logic gate of a logic circuit with first elem... | 06/04/2009 |
| 20090132221 | Verification of Highly Optimized Synchronous Pipelines via Random Simulation Driven by Critical Resource Scheduling System and Program Product Testing a model of a logic circuit model. The testing includes generating valid random input stimulus sequences for a logic circuit model. Enumerating critical resource requirements, enumerating critical resource availabilities does this, and selecting of stimulus seque... | 05/21/2009 |
| 20090112557 | System and Method of Automating the Addition of RTL Based Critical Timing Path Counters to Verify Critical Path Coverage of Post-Silicon Software Validation Tools A system and method for modifying a simulation model and optimizing an application program to produce valid hardware-identified operating conditions that are matched with simulator-identified operating conditions in order to modify a simulator accordingly is presented. ... | 04/30/2009 |
| 20090106010 | TECHNIQUE FOR DIGITAL CIRCUIT FUNCTIONALITY RECOGNITION FOR CIRCUIT CHARACTERIZATION A method and system of digital circuit functionality recognition for circuit characterization is disclosed. In one embodiment, a method for determining the valid arcs includes receiving a truth table including state information associated with input pins and their assoc... | 04/23/2009 |
| 20090063121 | OPTIMIZATION OF DISPLAYED RF COVERAGE A method for optimizing RF coverage includes dividing a floor plan according to a plurality of grids. Radio frequency coverage for each of the plurality of grids is calculated to render a plurality of coverages. First data representative of the plurality of coverage gri... | 03/05/2009 |
| 20090055010 | Back annotation equipment, mask layout correcting equipment, back annotation method, program, recording medium, process for fabricating semiconductor integrated circuit The present invention provides a back annotation apparatus for determining the delay value of a logic cell used in a timing simulation in view of the changes in the properties of a transistor element to be disposed at a position overlapped with an electrode pad of a sem... | 02/26/2009 |
