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| Application No. | Application Title | Issue Date |
| 20120109617 | OPTIMIZATION OF ELECTRICAL COMPONENT PARAMETERS IN ENERGY STORAGE SYSTEM MODELS A method of predicting an electrochemical mapping parameter in a vehicle that derives at least a portion of its motive power from an energy storage system is provided. The method may comprise providing a plurality of electrochemical mapping parameter sources capable of ... | 05/03/2012 |
| 20120110529 | CLOCK DOMAIN CROSSING BUFFER Techniques are disclosed relating to detecting and minimizing timing problems created by clock domain crossing (CDC) in integrated circuits. In various embodiments, one or more timing parameters are associated with a path that crosses between clock domains in an integra... | 05/03/2012 |
| 20120081588 | PIXEL SENSOR CELL WITH HOLD NODE FOR LEAKAGE CANCELLATION AND METHODS OF MANUFACTURE AND DESIGN STRUCTURE A reference pixel sensor cell (e.g., global shutter) with hold node for leakage cancellation, methods of manufacture and design structure is provided. A pixel array includes one or more reference pixel sensor cells dispersed locally throughout active light sensing regio... | 04/05/2012 |
| 20120084067 | METHOD AND APPARATUS FOR SYNTHESIZING PIPELINED INPUT/OUTPUT IN A CIRCUIT DESIGN FROM HIGH LEVEL SYNTHESIS A method and apparatus for synthesizing pipelined input/output in a circuit design from high level synthesis is described. In one example, an operation is selected to be performed by a circuit, the operation including a plurality of partial operations of different types... | 04/05/2012 |
| 20120084066 | SYSTEM AND METHOD FOR EFFICIENT MODELING OF NPSKEW EFFECTS ON STATIC TIMING TESTS A computer-implemented method that simulates NPskew effects on a combination NFET (Negative Field Effect Transistor)/PFET (Positive Field Effect Transistor) semiconductor device using slew perturbations includes performing a timing test by a computing device, by: (1) ev... | 04/05/2012 |
| 20120084745 | Design Method for Non-Shrinkable IP Integration A method of designing integrated circuits includes providing a design of an integrated circuit at a first scale, wherein the integrated circuit includes a shrinkable circuit including a first intellectual property (IP); and a non-shrinkable circuit including a second IP... | 04/05/2012 |
| 20120072876 | METHOD AND APPARATUS FOR REDUCING X-PESSIMISM IN GATE-LEVEL SIMULATION AND VERIFICATION Methods and apparatuses are described for reducing or eliminating X-pessimism in gate-level simulation and/or formal verification. A system can identify a set of reconvergent inputs of a combinational block in a gate-level design. Next, the system can determine whether ... | 03/22/2012 |
| 20120049947 | METHOD AND DEVICE FOR MEASURING INTEGRATED CIRCUIT POWER SUPPLY NOISE AND CALIBRATION OF POWER SUPPLY NOISE ANALYSIS MODELS A method and device for measuring integrated circuit power supply noise and calibration of power supply noise analysis models. The method includes collecting power supply noise monitor data from an integrated circuit having one or more power supply noise monitors connec... | 03/01/2012 |
| 20120053923 | METHODS OF DESIGNING INTEGRATED CIRCUITS AND SYSTEMS THEREOF A method of designing an integrated circuit includes performing a pre-layout simulation of the integrated circuit. The pre-layout simulation is performed using a netlist generated from a process design kit (PDK) file. The PDK file includes a plurality of device model ca... | 03/01/2012 |
| 20120053913 | Electrical-Thermal Co-Simulation with Joule Heating and Convection Effects for 3D Systems In a method for simulating temperature and electrical characteristics within an circuit, a temperature of at least one volume within the circuit as a function of a resistance within the at least one volume is repeatedly calculated and the resistance as a function of the... | 03/01/2012 |
| 20120041748 | Design support apparatus and method A design support apparatus includes an extraction part, a creation part, and a correction part. The extraction part extracts from among a power supply layer and a ground layer a range related to a signal transmission of a pair of signal transmission circuit models dispo... | 02/16/2012 |
| 20120041747 | Dynamically Adjusting Simulation Fidelity Based on Checkpointed Fidelity State Mechanisms are provided for controlling a fidelity of a simulation of a system. A model of the system is received, the model of the system having a plurality of individual components of the system. Fidelity values are assigned to models of the individual components of t... | 02/16/2012 |
| 20120022846 | METHODS, SYSTEMS, AND ARTICLES OF MANUFACTURE FOR IMPLEMENTING ELECTRONIC CIRCUIT DESIGNS WITH ELECTRO-MIGRATION AWARENESS Disclosed are methods, systems, and articles of manufacture for implementing electronic circuit designs with electro-migration awareness. Some embodiments perform schematic level simulation(s) to determine electrical characteristics, identifies physical parasitics of a ... | 01/26/2012 |
| 20120022847 | COHERENT STATE AMONG MULTIPLE SIMULATION MODELS IN AN EDA SIMULATION ENVIRONMENT A circuit design is simulated in a simulation environment. When a simulation model in the simulation environment transfers state information to a second simulation model, the simulation environment receives the state information and makes it available to the second simu... | 01/26/2012 |
| 20120016652 | SYSTEM AND METHOD FOR FAST POWER GRID AND SUBSTRATE NOISE SIMULATION Systems and methods related to fast simulation of power supply networks and identification of a set of extrema (e.g., maxima or minima) waveforms associated with the power supply networks. In accordance with an embodiment, a method is provided for simulating an electric... | 01/19/2012 |
| 20120004896 | COMPONENT BEHAVIOR MODELING USING SEPARATE BEHAVIOR MODEL A behavior model is provided, which is configured to simulate one aspect of the behavior of a component apart from the component model for the component. The behavior model can be included in a circuit model used to simulate operation of a circuit. The circuit model can... | 01/05/2012 |
| 20110320183 | COMPUTING DEVICE AND METHOD FOR ANALYZING DIFFERENTIAL TRANSMISSION LINES PORT RELATIONSHIPS A computing device and a method determines port relationships of a differential transmission line of a circuit board according to an original scattering parameters file, which records scattering parameter values measured from ports of the differential transmission line ... | 12/29/2011 |
| 20110320160 | INTEGRATED CIRCUIT, SIMULATION APPARATUS AND SIMULATION METHOD The disclosed device performs a control of generating a test pattern for the delay test of LSI. The input pattern control circuit counts a cycle number of an input pattern supplied to a test object circuit, and stops supply of the input pattern to the test object circui... | 12/29/2011 |
| 20110313748 | METHOD OF SIMULATION AND DESIGN OF A SEMICONDUCTOR DEVICE The invention relates to a method of simulation of semiconductor devices, such as wide-bandgap devices. The method employs a device substitution technique and involves simulation of a device which is structurally similar to the target device, and for which it is relativ... | 12/22/2011 |
| 20110313749 | CIRCUIT CONSTANT ANALYSIS METHOD AND CIRCUIT SIMULATION METHOD OF EQUIVALENT CIRCUIT MODEL OF MULTILAYER CHIP INDUCTOR The occurrence of errors between circuit design using a circuit simulator and the actual circuit performance is quite adequately suppressed. Mutual inductance (Lm) between direct current inductance (L0) and inductance (L1) is connected in parallel to a ser... | 12/22/2011 |
| 20110313747 | Technology Computer-Aided Design (TCAD)-Based Virtual Fabrication A single finite element mesh is generated for predicting performance of an integrated circuit design. A plurality of sample points are identified for conducting a variability study on at least one parameter associated with the integrated circuit design. The sample point... | 12/22/2011 |
| 20110313738 | SYSTEM AND METHOD FOR CIRCUIT ANALYSIS Systems and methods related to fast simulation of power supply networks and identification of a set of extrema (e.g., maxima or minima) waveforms associated with the power supply networks. In accordance with an embodiment, a method is provided for estimating the worst c... | 12/22/2011 |
| 20110307234 | CIRCUIT SIMULATION METHOD AND CIRCUIT SIMULATION DEVICE The present invention provides a circuit simulation method of executing a high-precision circuit simulation. A voltage fluctuation analysis step at a gate level is executed (step S2). The voltage fluctuation analysis step at the gate level is executed on an entir... | 12/15/2011 |
| 20110307233 | COMMON SHARED MEMORY IN A VERIFICATION SYSTEM The debug system described in this patent specification provides a system that generates hardware elements from normally non-synthesizable code elements for placement on an FPGA device. This particular FPGA device is called a Behavior Processor. This Behavior Processor ... | 12/15/2011 |
| 20110307235 | EQUIVALENT CIRCUIT MODEL FOR MULTILAYER CHIP CAPACITOR, CIRCUIT CONSTANT ANALYSIS METHOD, PROGRAM, DEVICE, AND CIRCUIT SIMULATOR Improved equivalent circuits and circuit analysis using the same for a multiplayer capacitor are provided. In one aspect, the equivalent series capacitance C and part of the equivalent series resistance R of a basic equivalent circuit for a multiplayer chip capacitor ar... | 12/15/2011 |
| 20110307226 | Efficient Data Compression For Vector-Based Static Timing Analysis In a STA method, after accessing data sets regarding the IC, vectors of the data sets for STA can be generated. Each vector can include a base value and a plurality of tokens, wherein each token is quantized. For each vector, the data of the vector can be adjusted. Adju... | 12/15/2011 |
| 20110301932 | MOSFET MODEL OUTPUT APPARATUS AND METHOD, AND RECORDING MEDIUM In one embodiment, a MOSFET model output apparatus is configured to output a MOSFET model for a simulation of a semiconductor circuit. The apparatus includes a shape data input part configured to input shape data of a MOSFET. The apparatus further includes a parameter c... | 12/08/2011 |
| 20110288825 | METHOD AND SYSTEM FOR EQUIVALENCE CHECKING As part of the design process it is required to design circuits in order to reduce their power consumption. This is typically done by enabling or disabling flip-flops (FFs), however, such change in the circuit requires certain verification. As sequential clock gating ch... | 11/24/2011 |
| 20110282639 | Modeling of Non-Quasi-Static Effects During Hot Carrier Injection Programming of Non-Volatile Memory Cells A non-quasi-static model of the programming behavior of a floating-gate metal-oxide-semiconductor (MOS) transistor. This model is based on evaluation of a body current, for example determined as a function of voltages applied to the transistor from the circuit environme... | 11/17/2011 |
| 20110282478 | FINFET BOUNDARY OPTIMIZATION A method for generating a layout for a semiconductor device is disclosed. The method includes: receiving a first layout. A portion of the first layout is defined as a first FinFET region. The first FinFET region has first and second sides that each extend approximately ... | 11/17/2011 |
| 20110276321 | DEVICE SPECIFIC CONFIGURATION OF OPERATING VOLTAGE A method and circuit for device specific configuration of an operating voltage is provided. A circuit design is analyzed to determine a maximum gate-level delay for the circuit design. A minimum voltage value corresponding to the maximum gate-level delay is determined a... | 11/10/2011 |
| 20110270597 | Tracking Array Data Contents Across Three-Valued Read and Write Operations A mechanism is provided in an integrated circuit simulator for tracking array data contents across three-value read and write operations. The mechanism accounts for write operations with data values and address values having X symbols. The mechanism performs writes to a... | 11/03/2011 |
| 20110270598 | Integrated Circuit Design and Simulation An integrated circuit design method, system and simulator, wherein the integrated circuit design method includes: determining a region in which power supply noise shall be analyzed; determining current model parameters of the region; determining model parameters of a po... | 11/03/2011 |
| 20110264422 | AUTOMATION OF THE ZERO-POLE IDENTIFICATION METHODS FOR THE STABILITY ANALYSIS OF MICROWAVE ACTIVE CIRCUITS A method of analyzing electrical stability of an active circuit splits a frequency response of an electrical or electronic circuit according to sub-bands (134, 136, 138) and in each sub-band (134, 136, 138) implements a step of determining an identificatio... | 10/27/2011 |
| 20110257954 | Versatile Method and Tool for Simulation of Aged Transistors In an embodiment, an aging analysis tool may be configured to identify transistors that are expected to experience aging effects according to worst case stress vectors and/or designer identified worst case conditions. The aging analysis tool may modify a representation ... | 10/20/2011 |
| 20110257953 | SIMULATION TOOL FOR HIGH-SPEED COMMUNICATIONS LINKS A link simulation tool for simulating high-speed communications link systems is provided. Communications links may include link subsystems such as transmit (TX) circuitry, receive (TX) circuitry, oscillator circuits that provide reference clock signals to the TX and RX ... | 10/20/2011 |
| 20110257943 | NODE-BASED TRANSIENT ACCELERATION METHOD FOR SIMULATING CIRCUITS WITH LATENCY When modeling a circuit, transient analysis is an important part of the analysis. However, for transient analyses, device model evaluating can consume a considerable amount of time, when using conventional simulators. Here, a simulator is provided that allows for detect... | 10/20/2011 |
| 20110246169 | SYSTEM AND METHOD FOR SUPPORTING DESIGNING OF SEMICONDUCTOR DEVICE A semiconductor circuit designing supporting system, includes: a storage unit in which two models of a first model and a second model are stored as device models a semiconductor device; and an operation unit. The operating unit includes: a characteristic variation calcu... | 10/06/2011 |
| 20110239002 | DIFFERENTIAL UNCLONEABLE VARIABILITY-BASED CRYPTOGRAPHY Differential uncloneable variability-based cryptography techniques are provided. The differential cryptography includes a hardware based public physically uncloneable function (PPUF) to perform the cryptography. The PPUF includes a first physically uncloneable function ... | 09/29/2011 |
| 20110239182 | AUTOMATIC CIRCUIT DESIGN TECHNIQUE A set of pareto optimal solutions that are non-dominated solutions in a solution specification space for respective items in requirement specification is extracted with a combination of a circuit configuration including a specific function and a process constraint condi... | 09/29/2011 |
