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| Application No. | Application Title | Issue Date |
| 20120041707 | COLD BOOT TEST SYSTEM AND METHOD FOR ELECTRONIC DEVICES A cold boot test system and method can control an electronic device to perform a cold boot process to test whether the electronic device is operable. The method sets time parameters for a test period of the cold boot process, drives a data communication interface of a c... | 02/16/2012 |
| 20120016619 | DELAY FAULT TEST QUALITY CALCULATION APPARATUS, DELAY FAULT TEST QUALITY CALCULATION METHOD, AND DELAY FAULT TEST PATTERN GENERATION APPARATUS A delay fault test quality calculation apparatus for calculating delay fault test quality to be achieved by a test pattern to be applied to a semiconductor integrated circuit includes a defect distribution extraction unit, a delay fault-layout element information extrac... | 01/19/2012 |
| 20110301907 | Accelerating Automatic Test Pattern Generation in a Multi-Core Computing Environment via Speculatively Scheduled Sequential Multi-Level Parameter Value Optimization Systems and methods provide acceleration of automatic test pattern generation in a multi-core computing environment via multi-level parameter value optimization for a parameter set with speculative scheduling. The methods described herein use multi-core based parallel r... | 12/08/2011 |
| 20110178757 | ERROR ASSESSMENT METHOD FOR TEST STIMULUS SIGNAL OF ANALOG TO DIGITAL CONVERTER An error assessment method for a test stimulus signal of an analog to digital converter is disclosed. The method provides random uniform-distribution test signals for an analog to digital converter (ADC), derives the piecewise linearity relationship between the input si... | 07/21/2011 |
| 20110172945 | METHOD FOR MONITORING BURN-IN PROCEDURE OF ELECTRONIC DEVICE A method for monitoring a burn-in procedure of an electronic device is performed by a host computer, an external storage device, and a display device. The external storage device stores the burn-in procedure and a monitor procedure. The host computer copies the monitor ... | 07/14/2011 |
| 20110172946 | MULTIFUNCTIONAL DISTRIBUTED ANALYSIS TOOL AND METHOD FOR USING SAME A multi-function, intelligent, distributed analysis test tool (MFDAT) suitable for performing maintenance on complex, 5 sophisticated electronic systems. MFDAT replaces ordinary test instruments such as spectrum analyzers, oscilloscopes, power meters, frequency counters... | 07/14/2011 |
| 20110106482 | GENERATING A COMBINATION EXERCISER FOR EXECUTING TESTS ON A CIRCUIT A first and second test templates are combined to a combination test template. The combination test template may be configured to execute the first and second test templates in combination, and based upon a definition. The combination test template may execute tests in ... | 05/05/2011 |
| 20110035178 | SYSTEM AND METHOD FOR GENERATING A TEST FILE OF A PRINTED CIRCUIT BOARD A system and method generates a test file of a print circuit board (PCB). The system and method loads trace information of the PCB into a storage system of a test computer, searches the storage system for the trace information matching keywords received and selects trac... | 02/10/2011 |
| 20100324855 | SYSTEMS AND METHODS FOR REMOTE ELECTRONICS DEVICE TESTING Testing systems and methods are operable to perform diagnostic testing of a remote electronic device under test (DUT). An exemplary embodiment establishes a communication link between a diagnostic test device and the electronic DUT, receives a plurality of diagnostic co... | 12/23/2010 |
| 20100312517 | Test Method Using Memory Programmed with Tests and Protocol To Communicate between Device Under Test and Tester In an embodiment, a test method is implemented to test an integrated circuit that includes at least one processor. The method may include programming a memory to which the integrated circuit is coupled during testing with one or more test programs. The integrated circui... | 12/09/2010 |
| 20100256933 | METHOD OF DETECTING CHANGES IN INTEGRATED CIRCUITS USING THERMALLY IMAGED TEST PATTERNS A method of testing an electrical circuit includes applying test vectors to a circuit, detecting thermal changes in portions of the circuit during application of the test vectors, and identifying unexpected activity corresponding to the thermal changes. The method suppl... | 10/07/2010 |
| 20100235135 | General Purpose Protocol Engine In one embodiment, a protocol aware circuit for automatic test equipment, which includes a protocol generation circuit constructed to retrieve protocol unique data and format the protocol unique data with a selected protocol definition corresponding to a device under te... | 09/16/2010 |
| 20100153053 | Stream Based Stimulus Definition and Delivery via Interworking An approach is provided to manage test transactors that interface with components of a hardware design. A first set of transactors is launched with the first set sending stimuli to various components that correspond to the first set of transactors. A manager receives si... | 06/17/2010 |
| 20100082283 | TESTING DEVICE FOR PORTABLE ELECTRONIC DEVICES A testing device for portable electronic devices includes a processor storing test programs corresponding to various portable electronic devices, a control module connected to the processor, and a testing apparatus connected to the control module and connecting to teste... | 04/01/2010 |
| 20100070230 | INTEGRATED TESTING SYSTEMS AND METHODS An exemplary method includes parsing data representative of an automated test case into at least one transaction defined in accordance with a global test language, translating the transaction into at least one command specific to an automated test tool, and providing th... | 03/18/2010 |
| 20100042353 | SYSTEM AND METHOD FOR TESTING WORKING CONDITION OF LED INDICATORS ON HARD DISK DRIVES A method is provided to test working condition of LED indicators on hard disk drives connected to a computer. The method calls an API function from an operating system of the computer to create a main thread, and creates a sub thread for each of the hard disk drives con... | 02/18/2010 |
| 20100042354 | Measuring Device with Serial Digital Interface The invention relates to a measuring device having at least one first assembly and at least one second assembly. The first assembly and the second assembly each comprise an intermediate frequency interface or a complex baseband interface. The intermediate frequency inte... | 02/18/2010 |
| 20090326854 | TESTING STATE RETENTION LOGIC IN LOW POWER SYSTEMS A method of testing an Integrated Circuit (IC) includes: loading a sequence of data into a chain of circuit elements that hold data values, where outputs of at least some circuit elements are connected to inputs of adjacent circuit elements so values move sequentially t... | 12/31/2009 |
| 20090299679 | Method of Adaptively Selecting Chips for Reducing In-line Testing in a Semiconductor Manufacturing Line A method for identifying potentially defective integrated circuit chips and excluding them from future testing as wafers move through a manufacturing line The method includes data-collecting steps, tagging the chips on wafers identified as potentially bad chips based on... | 12/03/2009 |
| 20090299678 | METHOD AND APPARATUS FOR DETERMINING A PRODUCT LOADING PLAN FOR A TESTING SYSTEM A method for determining a loading plan for a testing system includes determining demand quotas for a plurality of devices to be processed through the testing system. Each demand quota specifies a number of required devices and an associated performance specification. A... | 12/03/2009 |
| 20090299680 | System and method for message-queue-based server testing A system for testing a banking transactions server. The system includes a storage medium storing a plurality a simulated banking transactions. The system also includes a script engine executing on a processor. The system also includes a plurality of templates useable by... | 12/03/2009 |
| 20090240457 | TESTING IN A HARDWARE EMULATION ENVIRONMENT A system and method is disclosed for testing emulation boards in a hardware emulation environment. In one embodiment, test files can be maintained that identify a list of test commands. Such a list can be easily changed without recompiling. In another embodiment, the li... | 09/24/2009 |
| 20090222234 | Generating Worst Case Test Sequences For Non-Linearly Driven Channels Various implementations of the invention provide methods and apparatuses for generating a test sequence for a driver and channel combination, wherein the driver is non-linear. In various implementations of the invention, a test sequence is generated that produces the wo... | 09/03/2009 |
| 20090187368 | Burn-In Tests To Produce Fabricated Integrated Circuits With Reduced Variations Due To Process Spread An aspect of the present invention enables burn-in tests to reduce variations due to process spread in fabricated integrated circuits (IC). Fabricated ICs are classified into multiple categories based on performance characteristics (e.g., operational speed) indicative o... | 07/23/2009 |
| 20090144675 | TRANSACTION BASED VERIFICATION OF A SYSTEM ON CHIP ON SYSTEM LEVEL BY TRANSLATING TRANSACTIONS INTO MACHINE CODE In a transaction-based verification environment for complex semiconductor devices, enhanced verification efficiency may be achieved by providing a transaction to machine code translator and an appropriate interface that enables access of the translated machine code inst... | 06/04/2009 |
| 20090119054 | TEST EQUIPMENT, METHOD FOR LOADING TEST PLAN AND PROGRAM PRODUCT The test equipment includes a memory to which a test plan consisting of a plurality of sub-test plans is loaded; and a controller that loads the test plan to the memory by the unit of the sub-test plan and supplies a test signal to the DUT by interpreting the loaded tes... | 05/07/2009 |
| 20090048800 | TEST INSTRUMENT NETWORK A test instrument network for testing a plurality of DUTs includes a plurality of communicating script processors, the script processors being adapted to execute computer code; and a plurality of measurement resources controllable by the script processors in response to... | 02/19/2009 |
| 20090037132 | Parallel Test System A method and a system for defining groups of tests that may be concurrently performed or overlapped are provided. Channel-independent test groups are determined such that each group includes tests that the input/output channels may be utilized simultaneously without con... | 02/05/2009 |
| 20080313006 | SYSTEMS, METHODS, AND DEVICES FOR MANAGING EMERGENCY POWER SUPPLY SYSTEMS Aspects of the present disclosure generally relate to systems and methods for managing and monitoring a plurality of emergency power supply systems (EPSS's) at a facility via an emergency power management system (EPMS). The EPMS generally comprises EPSS equipment, a man... | 12/18/2008 |
| 20080281545 | DETERMINING DIE TEST PROTOCOLS BASED ON PROCESS HEALTH A method includes receiving a first set of parameters associated with a subset of a plurality of die on a wafer. A die health metric is determined for at least a portion of the plurality of die based on the first set of parameters. The die health metric includes at leas... | 11/13/2008 |
| 20080275662 | Generating transmission-code compliant test sequences Disclosed herein are exemplary methods, apparatus, and systems for generating test sequences that can be used to evaluate high-speed circuit pathways. The disclosed methods, apparatus, and systems can be used, for example, in a printed circuit board or integrated circui... | 11/06/2008 |
| 20080270065 | AUTOMATED SIMULATION TESTBENCH GENERATION FOR SERIALIZER/DESERIALIZER DATAPATH SYSTEMS Embodiments herein present a method for automated simulation testbench generation for serializer/deserializer datapath systems. The method provides a database of transactors for generating and checking data within the datapath system, wherein the transactors are adaptab... | 10/30/2008 |
| 20080270064 | M1 Testable Addressable Array for Device Parameter Characterization An integrated circuit device and device parameter characterization method are provided. The integrated circuit device has a padset with plurality of pads. The integrated circuit device also includes one or more arrays of devices under test, each of the one or more array... | 10/30/2008 |
| 20080262778 | RECORDING MEDIUM, TEST APPARATUS AND PROGRAM A recording medium recording thereon a program for a test apparatus including test modules that test devices under test is provided. The program includes: a common function provision program which is executed on a controller for controlling the test apparatus and provid... | 10/23/2008 |
| 20080255791 | INTERFACE TO FULL AND REDUCE PIN JTAG DEVICES The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced pin JTAG devices (506), or a mixture of both full pin and reduced pin JTAG devices. The access i... | 10/16/2008 |
| 20080255792 | TEST SYSTEM AND COMPUTER PROGRAM FOR DETERMINING THRESHOLD VOLTAGE VARIATION USING A DEVICE ARRAY A test system and computer program for measuring threshold voltage variation using a device array provides accurate threshold voltage distribution values for process verification and improvement. The test system and computer program control a characterization array circ... | 10/16/2008 |
| 20080234967 | Test Sequence Optimization Method and Design Tool A method for defining a sequence of tests for testing a plurality of electronic devices including integrated circuits is disclosed. A reference group of devices is defined (110), after which the devices in said group are subjected to all available tests under con... | 09/25/2008 |
| 20080195346 | Low power scan testing techniques and apparatus Disclosed below are representative embodiments of methods, apparatus, and systems used to reduce power consumption during integrated circuit testing. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a vari... | 08/14/2008 |
| 20080183416 | Semiconductor integrated circuit A semiconductor integrated circuit having a test circuit for collecting test data at any time based on interaction with an external source is provided. A communication circuit receives a data frame that is transferred to a data buffer. Data portions are transferred to a... | 07/31/2008 |
| 20080143370 | I/O PORT TESTER An I/O port tester includes a first relay, a second relay, a first resistor, a second resistor, a plurality of serial plugs, a water sensor plug, a direct current (DC) voltage plug, and two data plugs. A half of the serial plugs is correspondingly connected to the other... | 06/19/2008 |
