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| Application No. | Application Title | Issue Date |
| 20120130669 | VARIATION AWARE TESTING OF SMALL RANDOM DELAY DEFECTS In one embodiment, the invention is a method and apparatus for variation aware testing of small random delay defects. One embodiment of a method for selecting a set of paths with which to test an integrated circuit chip includes computing a metric that considers the joi... | 05/24/2012 |
| 20120053882 | DATA TRANSFER CIRCUIT, SOLID-STATE IMAGING DEVICE, AND CAMERA SYSTEM A data transfer circuit includes at least one data transfer line that transfers digital data, at least one data detecting circuit connected to the transfer line, holding circuits that hold digital values corresponding to input levels and that transfer the digital values... | 03/01/2012 |
| 20120053924 | SYSTEM AND METHOD FOR EXECUTING FUNCTIONAL SCANNING IN AN INTEGRATED CIRCUIT ENVIRONMENT An example method is provided and includes executing a functional test for an integrated circuit and observing a failure associated with the integrated circuit. The method also includes executing a functional scan mode in order to reproduce the failure associated with t... | 03/01/2012 |
| 20120035877 | SEMICONDUCTOR DEVICE HAVING TEST FUNCTION AND TEST METHOD USING THE SAME A semiconductor device having a test function includes a program counter for storing a breaking address in a storage unit in response to control signals, increasing a count address in response to the control signals, and storing the increased count address in the storag... | 02/09/2012 |
| 20120029861 | SEMICONDUCTOR CIRCUIT, SEMICONDUCTOR CIRCUIT TEST METHOD, AND SEMICONDUCTOR CIRCUIT TEST SYSTEM In general, according to one embodiment, a semiconductor circuit test method is disclosed. The method can generate a basic format of a test pattern and store the basic format in a test device. The basic format includes at least one parameter and a test program for testi... | 02/02/2012 |
| 20120029860 | TEST CIRCUIT FOR NETWORK INTERFACE A first output pin of a microcontroller is connected to a control pin of a high speed switch chip. A second output pin of the microcontroller is connected to two control pins of first and second switch chips. Two output pins of the high speed switch chip are connected t... | 02/02/2012 |
| 20110313708 | METHODS FOR MANUFACTURING DEVICES WITH FLEX CIRCUITS AND RADIO-FREQUENCY CABLES A flex circuit may have test structures and antenna structures. The test structures may include test capacitors and transmission lines. The performance of the test structures may be measured using test equipment. Pass/fail criteria may be applied to the flex circuit bas... | 12/22/2011 |
| 20110313709 | POWER CIRCUIT ANALYSIS APPARATUS AND METHOD A power circuit analysis apparatus includes a segmentation unit that segments an analysis target region in a power circuit included in an analysis target circuit into a plurality of segmented regions, and an analysis unit that outputs an analysis result of the power cir... | 12/22/2011 |
| 20110288807 | FAILURE DETECTING METHOD, SEMICONDUCTOR DEVICE, AND MICROCOMPUTER APPLICATION SYSTEM The present invention is directed to improve the precision of failure detection by performing the failure detection by changing an analog amount of a circuit to be subjected to the failure detection. An analog amount of the circuit to be subjected to failure detection i... | 11/24/2011 |
| 20110282616 | TEST APPARATUS AND TEST METHOD Provided is a test apparatus that tests a device under test, comprising a control apparatus that controls testing of the device under test; a test unit that sends and receives signals to and from the device under test; and a buffer section that buffers access requests t... | 11/17/2011 |
| 20110276302 | RE-CONFIGURABLE TEST CIRCUIT, METHOD FOR OPERATING AN AUTOMATED TEST EQUIPMENT, APPARATUS, METHOD AND COMPUTER PROGRAM FOR SETTING UP AN AUTOMATED TEST EQUIPMENT A re-configurable test circuit for use in an automated test equipment includes a test circuit, a test processor and a programmable logic device. The pin electronics circuit is configured to interface the re-configurable test circuit with a DUT. The test processor includ... | 11/10/2011 |
| 20110275170 | SYSTEM FOR CONCURRENT TEST OF SEMICONDUCTOR DEVICES A tool to aid a test engineer in creating a concurrent test plan. The tool may quickly map test system resources to specific pins to satisfy the requirements of a concurrent test. The tool may project test time when such a mapping is possible. When a mapping is not poss... | 11/10/2011 |
| 20110264396 | ELECTRICAL CIRCUIT WITH PHYSICAL LAYER DIAGNOSTICS SYSTEM An electrical circuit has a power supply, one or more devices and a diagnostics system. The diagnostics system includes a monitoring means adapted to monitor physical layer characteristics of the electrical circuit, a database containing circuit design data for the elec... | 10/27/2011 |
| 20110257923 | WiFi Positioning Bench Test Method and Instrument The present invention relates to simulation on a lab workbench of conditions that would be encountered by a mobile device during a so-called drive test, which involves transporting the mobile device along a course so that it encounters fading and changing wireless acces... | 10/20/2011 |
| 20110246119 | PROCESS FOR TESTING THE RESISTANCE OF AN INTEGRATED CIRCUIT TO A SIDE CHANNEL ANALYSIS A process for testing an integrated circuit includes collecting a set of points of a physical property while the integrated circuit is executing a multiplication, dividing the set of points into a plurality subsets of lateral points, calculating an estimation of the val... | 10/06/2011 |
| 20110246120 | EQUIVALENT CIRCUIT OF INDUCTANCE ELEMENT, METHOD OF ANALYZING CIRCUIT CONSTANT, CIRCUIT CONSTANT ANALYSIS PROGRAM, DEVICE FOR ANALYZING CIRCUIT CONSTANT, CIRCUIT SIMULATOR The present invention provides an equivalent circuit, circuit constant analysis method, circuit constant analysis program, circuit constant analysis device, and circuit simulator for an inductance element that are capable of good approximation of characteristics even in... | 10/06/2011 |
| 20110218755 | INTEGRATED CIRCUIT AND TEST METHOD THEREFOR Disclosed is a method of testing an integrated circuit (100) comprising a radio-frequency (RF) transceiver, said transceiver comprising a receiver chain (120) having an input for coupling the receiver chain to an antenna (112) and an output coupled ... | 09/08/2011 |
| 20110210759 | FAST OPEN CIRCUIT DETECTION FOR OPEN POWER AND GROUND PINS A system and method for identifying opens among parallel connections on a circuit assembly such as a printed circuit board (PCB). In a learn phase performed on a known good circuit assembly, a group of parallel connected pins are excited with a first signal. A second si... | 09/01/2011 |
| 20110208467 | CALIBRATION STANDARDS AND METHODS OF THEIR FABRICATION AND USE An embodiment of a calibration standard includes a substrate, a set of conductive structures fabricated on the substrate, and a conductive end structure fabricated on the substrate. The set of conductive structures include an inner conductive structure, a first outer co... | 08/25/2011 |
| 20110196641 | Semiconductor device and diagnostic method thereof A semiconductor device includes a test target circuit subjected to self-diagnosis, a PLL circuit that outputs a clock for the self-diagnosis to the test target circuit, a diagnostic register that stores a clock frequency corresponding to an operation speed limit of the ... | 08/11/2011 |
| 20110191055 | METHOD AND APPARATUS FOR SELECTING VOLTAGE AND FREQUENCY LEVELS FOR USE IN AT-SPEED TESTING In one embodiment, the invention is a method and apparatus for selecting voltage and frequency levels for use in at-speed testing. One embodiment of a method for selecting a set of test conditions with which to test an integrated circuit chip includes formulating a stat... | 08/04/2011 |
| 20110166818 | LOW POWER SCAN TESTING TECHNIQUES AND APPARATUS Disclosed below are representative embodiments of methods, apparatus, and systems used to reduce power consumption during integrated circuit testing. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a vari... | 07/07/2011 |
| 20110161040 | COMPUTER SYSTEM ON AND OFF TEST APPARATUS A computer system on/off test apparatus includes a parameter setting and test control circuit, a test indicating circuit, a voltage converting circuit, and an on/off signal switch circuit. The parameter setting and test control circuit includes a micro control unit (MCU... | 06/30/2011 |
| 20110137603 | Enforcing Worst-Case Behavior During Transmit Channel Analysis Techniques for analyzing the signal integrity of a channel by enforcing a worst-case behavior during the analysis are presented. Initially a channels response to an input bit sequence, followed by a test bit sequence is simulated. Subsequently, a pulse response is extra... | 06/09/2011 |
| 20110137602 | INSERTION OF FAULTS IN LOGIC MODEL USED IN SIMULATION A method of selecting fault candidates based on the physical layout of an Integrated Circuit (IC) layout, that includes, identifying failing observation points in an IC layout, determining the failing observation points proximity geometry in the IC circuit layout, deter... | 06/09/2011 |
| 20110137604 | REAL-TIME ADAPTIVE HYBRID BiST SOLUTION FOR LOW-COST AND LOW-RESOURCE ATE PRODUCTION TESTING OF ANALOG-TO-DIGITAL CONVERTERS An integrated circuit configured to perform hybrid built in self test (BiST) of analog-to-digital converters (ADCs) is described. The integrated circuit includes an ADC. The integrated circuit also includes a BiST controller that controls the hybrid BiST. The integrated... | 06/09/2011 |
| 20110130999 | TEST SYSTEM FOR CONNECTORS A test system includes a main selector, a first and a second switching connectors, a first and a second sub-selectors, and a processor. The main selector includes a number of first switches, a number of first contacts, and a number of second contacts. Each sub-selector ... | 06/02/2011 |
| 20110106481 | SYSTEM AND METHOD FOR CHECKING GROUND VIAS OF A CONTROLLER CHIP OF A PRINTED CIRCUIT BOARD A system and method for checking a ground via of control chips of a printed circuit board (PCB) provides a graphical user interface (GUI) displaying a layout of the PCB. The control chip has a plurality of ground pins. The computer searches for signal path routing of ea... | 05/05/2011 |
| 20110087452 | TEST DEVICE A test device for testing a system, which has first interface circuit, second interface circuit, and a power switch, comprises a power supply, status detector, and a controller. The power supply includes a supplying unit and a switch controller. The supplying unit provi... | 04/14/2011 |
| 20110087453 | RELIABILITY TEST WITH MONITORING OF THE RESULTS An embodiment for executing a reliability test is proposed. A corresponding electronic device includes functional means for implementing a functionality of the electronic device, and testing means for executing a test of the functional means including a plurality of tes... | 04/14/2011 |
| 20110077893 | Delay Test Apparatus, Delay Test Method and Delay Test Program A delay test apparatus for a semiconductor integrated circuit includes (1) a selecting unit that selects at least one pair of a beginning latch and an ending latch based on layout information of the semiconductor integrated circuit, the pair of the beginning latc... | 03/31/2011 |
| 20110066419 | Method to Simulate a Digital System A simulator is partitioned into a functional component and a behavior prediction component and the components are executed in parallel. The execution path of the functional component is used to drive the behavior prediction component and the behavior prediction componen... | 03/17/2011 |
| 20110040516 | TEST APPARATUS AND TEST METHOD FOR UNIVERSAL SERIAL BUS INTERFACE A test apparatus for testing USB interfaces of an electronic device. The test apparatus includes a number of USB interfaces connected to the USB interfaces of the electronic device via cables respectively, to communicate with the electronic device. A memory stores a spe... | 02/17/2011 |
| 20110035177 | DISTRIBUTED COMPUTING On a typical motherboard the processor and memory are separated by a printed circuit data bus that traverses the motherboard. Throughput, or data transfer rate, on the data bus is much lower than the rate at which a modern processor can operate. The difference between t... | 02/10/2011 |
| 20110035176 | APPARATUS FOR AUTOMATICALLY TESTING INTEGRATED CMOS MAGNETORESISTIVE BIOCHIPS An apparatus for automatically testing CMOS magnetoresistive biochips is disclosed. The apparatus includes: means for directly or indirectly applying physical pressure to the fluid pumping chamber in a cartridge; a liquid injector for injecting liquid into the reaction ... | 02/10/2011 |
| 20110018548 | PRINTED CIRCUIT BOARD TEST ASSISTING APPARATUS, PRINTED CIRCUIT BOARD TEST ASSISTING METHOD, AND COMPUTER-READABLE INFORMATION RECORDING MEDIUM A printed circuit board test assisting apparatus includes an input part that has the attribute information of the wiring pattern input thereto; a degradation degree process part that obtains a degradation degree in signal characteristics in a wiring pattern correspondin... | 01/27/2011 |
| 20110010126 | HIGH VOLTAGE INTERLOCK STRATEGY A High Voltage Interlock Strategy (HVIS) uses feedback current to detect cable connectivity status for a high-voltage cable configured to connect a power conversion circuit with a remote permanent magnet synchronous machine (PMSM). One or more feedback factors are calcu... | 01/13/2011 |
| 20100332169 | SYSTEM AND METHOD FOR TESTING A CHARACTERISTIC IMPEDANCE OF A SIGNAL PATH ROUTING OF A PRINTED CIRCUIT BOARD A method for testing a characteristic impedance of a signal path routing of a printed circuit board (PCB) controls the test device to test a characteristic impedance of the signal path routing of the PCB to get test data of the signal path routing of the PCB. The method... | 12/30/2010 |
| 20100332177 | TEST ACCESS CONTROL APPARATUS AND METHOD THEREOF A test access control apparatus includes test access mechanism (TAM) buses and an extended IEEE 1149.1 Test Access Port (TAP) Controller. The TAM buses support memory built-in-self-test (BIST) circuit for the memory known-good-die (KGD) test, scan chains for the logic K... | 12/30/2010 |
| 20100318313 | MEASUREMENT METHODOLOGY AND ARRAY STRUCTURE FOR STATISTICAL STRESS AND TEST OF RELIABILTY STRUCTURES System and method for obtaining statistics in a fast and simplified manner at the wafer level while using wafer-level test equipment. The system and method performs a parallel stress of all of the DUTs on a given chip to keep the stress time short, and then allows each ... | 12/16/2010 |
