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| Application No. | Application Title | Issue Date |
| 20120108020 | LOW TEMPERATURE COEFFICIENT RESISTOR IN CMOS FLOW A method for adding a low TCR resistor to a baseline CMOS manufacturing flow. A method of forming a low TCR resistor in a CMOS manufacturing flow. A method of forming an n-type and a p-type transistor with a low TCR resistor in a CMOS manufacturing flow.... | 05/03/2012 |
| 20120109356 | Method and Digital Circuit for Recovering a Clock and Data from an Input Signal Using a Digital Frequency Detection In a particular embodiment, a digital circuit includes a frequency detection circuit operative to compare information related to transitions between sequential samples of a received signal. The frequency detection circuit is further operative to generate a control signa... | 05/03/2012 |
| 20120046781 | METHOD, APPARATUS AND SYSTEM FOR USE IN PROCESSING WAFERS The present embodiment provides for methods and systems for use in processing objects such as wafers, including polishing and/or grinding wafers. Some embodiments provide systems that include a front-end module and a processing module. The front end module couples with ... | 02/23/2012 |
| 20120024222 | SUBSTRATE TEMPERATURE ACCURACY AND TEMPERATURE CONTROL FLEXIBILITY IN A MOLECULAR BEAM EPITAXY SYSTEM A control system and method for controlling temperatures while performing a MBE deposition process, wherein the control system comprises a MBE growth structure; a heater adapted to provide heat for the MBE deposition process on the MBE growth structure; and a control co... | 02/02/2012 |
| 20120016510 | DEVICE AND METHOD FOR CONTROLLING SUPPLY VOLTAGE/FREQUENCY USING INFORMATION OF PROCESS VARIATION A device capable of controlling a supply voltage and a supply frequency using information of a manufacturing process variation includes a data storage device storing data indicating performance of the device, a decoder decoding the data stored in the data storage device... | 01/19/2012 |
| 20120016509 | Semiconductor Processing Dispatch Control An embodiment is a method for semiconductor processing control. The method comprises identifying a key process stage from a plurality of process stages based on a parameter of processed wafers, forecasting a trend for a wafer processed by the key process stage and some ... | 01/19/2012 |
| 20120004896 | COMPONENT BEHAVIOR MODELING USING SEPARATE BEHAVIOR MODEL A behavior model is provided, which is configured to simulate one aspect of the behavior of a component apart from the component model for the component. The behavior model can be included in a circuit model used to simulate operation of a circuit. The circuit model can... | 01/05/2012 |
| 20120002334 | ELECTROSTATIC DISCHARGE CIRCUIT An integrated circuit (IC) is disclosed. The IC includes a first global voltage node and a second global voltage node. The IC further includes two or more power domains each coupled to the first global voltage node. Each of the two or more power domains includes a funct... | 01/05/2012 |
| 20120003761 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE AND FABRICATION SYSTEM OF SEMICONDUCTOR DEVICE A method of fabricating a semiconductor device and a fabrication system of the semiconductor device are provided. The method includes sequentially forming a film to be etched and a dielectric film and measuring a thickness of the dielectric film, forming a photoresist f... | 01/05/2012 |
| 20110320030 | Thermal Control of a Proximity Mask and Wafer During Ion Implantation An improved method of processing substrates, such as to create solar cells, is disclosed. The use of shadow masks may cause alignment errors associated with the differing thermal expansion characteristics of the shadow mask and the substrate. To counteract this error, m... | 12/29/2011 |
| 20110309152 | PLASTIC CARD PACKAGE AND PLASTIC CARD PACKAGE MANUFACTURING METHOD A plastic card package and a method of manufacturing the plastic card package are provided. The plastic card package includes: a socket insertion area that is formed to expose an I/O terminal corresponding to a contact terminal of a socket electrically connected to a pr... | 12/22/2011 |
| 20110307088 | Auto Device Skew Manufacturing A system and method for manufacturing semiconductor devices is disclosed. An embodiment comprises using desired device parameters to choose an initial manufacturing recipe. Once chosen, the initial manufacturing recipe may be modified by determining and applying an offs... | 12/15/2011 |
| 20110301736 | APC Model Extension Using Existing APC Models A method of extending advanced process control (APC) models includes constructing an APC model table including APC model parameters of a plurality of products and a plurality of work stations. The APC model table includes empty cells and cells filled with existing APC m... | 12/08/2011 |
| 20110282478 | FINFET BOUNDARY OPTIMIZATION A method for generating a layout for a semiconductor device is disclosed. The method includes: receiving a first layout. A portion of the first layout is defined as a first FinFET region. The first FinFET region has first and second sides that each extend approximately ... | 11/17/2011 |
| 20110241741 | SYSTEM AND METHOD TO CONTROL A POWER ON RESET SIGNAL A system and method to control a power on reset signal is disclosed. In a particular embodiment, a power on reset circuit includes a first linear feedback shift register and a second linear feedback shift register. The first linear feedback shift register is configured ... | 10/06/2011 |
| 20110245948 | Method And Circuit To Generate Race Condition Test Data At Multiple Supply Voltages A method and circuit for characterizing a process variation of a semiconductor die is disclosed. In a particular embodiment, the method includes operating a circuit at multiple supply voltage levels to generate race condition testing data. The circuit is disposed on at ... | 10/06/2011 |
| 20110238198 | METHOD AND SYSTEM FOR IMPLEMENTING VIRTUAL METROLOGY IN SEMICONDUCTOR FABRICATION The present disclosure provides a method of fabricating a semiconductor device. The method includes collecting a plurality of manufacturing data sets from a plurality of semiconductor processes, respectively. The method includes normalizing each of the manufacturing dat... | 09/29/2011 |
| 20110238203 | Method and Apparatus to Provide a Clock Signal to a Charge Pump A method and apparatus for providing a clock signal to a charge pump is disclosed. In a particular embodiment, the method includes providing a first clock signal to a first charge pump unit of a charge pump. The method further includes providing a second clock signal to... | 09/29/2011 |
| 20110238197 | DYNAMIC COMPENSATION IN ADVANCED PROCESS CONTROL A method of semiconductor fabrication is provided. The method includes providing a model for a device parameter of a wafer as a function of first and second process parameters. The first and second process parameters correspond to different wafer characteristics, respec... | 09/29/2011 |
| 20110198677 | SYSTEMS AND METHODS FOR A CONTINUOUS-WELL DECOUPLING CAPACITOR A decoupling capacitor includes a pair of MOS capacitors formed in wells of opposite plurality. Each MOS capacitor has a set of well-ties and a high-dose implant, allowing high frequency performance under accumulation or depletion biasing. The top conductor of each MOS ... | 08/18/2011 |
| 20110190924 | CONTROL DEVICE FOR CONTROLLING SUBSTRATE PROCESSING APPARATUS AND METHOD THEREFOR An EC includes a substrate processing execution unit that executes an etching process on a product substrate, a dummy processing execution unit that executes a dummy process on a dummy substrate and a decision-making unit that makes a decision as to whether the dummy pr... | 08/04/2011 |
| 20110184548 | ELECTRONIC COMPONENT MOUNTING MACHINE AND OPERATING INSTRUCTION METHOD FOR THE SAME A challenge to be met by the invention is to provide an electronic component mounting machine that makes up an electronic component mounting line and that standardizes an operation input method, to thus enable lessening of work load on an operator during performance of ... | 07/28/2011 |
| 20110178624 | RULE-BASED ROOT CAUSE AND ALIAS ANALYSIS FOR SEMICONDUCTOR MANUFACTURING The present invention includes a computing system determining a best alias rule in a semiconductor manufacturing process. The computing system obtains an original rule and candidate alias rules based on sampled data from the semiconductor manufacturing process. The comp... | 07/21/2011 |
| 20110163416 | METHODS FOR FORMING SMALL-SCALE CAPACITOR STRUCTURES The present disclosure provides small scale capacitors (e.g., DRAM capacitors) and methods of forming such capacitors. One exemplary implementation provides a method of fabricating a capacitor that includes sequentially forming a first electrode, a dielectric layer, and... | 07/07/2011 |
| 20110159676 | FABRICATING LOW CONTACT RESISTANCE CONDUCTIVE LAYER IN SEMICONDUCTOR DEVICE A conductive layer may be fabricated on a semiconductor substrate by loading a silicon substrate in to a chamber whose inside temperature is at a loading temperature in the range of approximately 250° C. to approximately 300° C., increasing the inside temperature of t... | 06/30/2011 |
| 20110159436 | METHOD AND SYSTEM FOR FRACTURING A PATTERN USING CHARGED PARTICLE BEAM LITHOGRAPHY WITH MULTIPLE EXPOSURE PASSES In the field of semiconductor production using charged particle beam lithography, a method and system for fracturing or mask data preparation or proximity effect correction is disclosed, wherein a plurality of exposure passes are used, and where the sum of the base dosa... | 06/30/2011 |
| 20110159434 | METHOD AND SYSTEM FOR FRACTURING A PATTERN USING CHARGED PARTICLE BEAM LITHOGRAPHY WITH MULTIPLE EXPOSURE PASSES HAVING DIFFERENT DOSAGES In the field of semiconductor production using charged particle beam lithography, a method and system for fracturing or mask data preparation or proximity effect correction is disclosed, wherein base dosages for a plurality of exposure passes are different from each oth... | 06/30/2011 |
| 20110159435 | METHOD AND SYSTEM FOR FRACTURING A PATTERN USING CHARGED PARTICLE BEAM LITHOGRAPHY WITH MULTIPLE EXPOSURE PASSES WHICH EXPOSE DIFFERENT SURFACE AREA In the field of semiconductor production using charged particle beam lithography, a method and system for fracturing or mask data preparation or proximity effect correction is disclosed, in which the union of shots from one of a plurality of exposure passes is different... | 06/30/2011 |
| 20110153055 | WIDE-RANGE QUICK TUNABLE TRANSISTOR MODEL A method includes selecting one of a plurality of existing transistor models for which fabrication and performance data are available, receiving first model data for a next-generation transistor based on target response data and the selected transistor model data, and s... | 06/23/2011 |
| 20110132650 | High-Speed Ceramic Modules with Hybrid Referencing Scheme for Improved Performance and Reduced Cost A multi-layered ceramic package comprises: a signal layer with identified chip/device area(s)/site(s) that require a supply of power; and a voltage power (Vdd) layer and a ground (Gnd) layer disposed on opposite sides directly above or below (adjacent to) the signal lay... | 06/09/2011 |
| 20110130861 | SEMICONDUCTOR MANUFACTURING APPARATUS AND CONTROL SYSTEM AND CONTROL METHOD THEREFOR Disclosed herein is technology for, among other things, a semiconductor manufacturing apparatus, and a control system and a control method therefor, by which a target parameter that is measured from a wafer processed with a plurality of processing parameters that are pr... | 06/02/2011 |
| 20110130860 | Registration System and Method Printed circuit boards are manufactured by forming a composite layer using a control system which models a production process to generate data using non-linear compensation techniques to compensate for non-linear distortion occurring in a circuit layout applied to a con... | 06/02/2011 |
| 20110124193 | CUSTOMIZED PATTERNING MODULATION AND OPTIMIZATION The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes providing an IC design layout of a circuit; applying an electrical patterning (ePatterning) modification to the IC design layout according to an electrical pa... | 05/26/2011 |
| 20110125308 | APPARATUS FOR MANUFACTURING SUBSTRATE FOR TESTING, METHOD FOR MANUFACTURING SUBSTRATE FOR TESTING AND RECORDING MEDIUM A test substrate manufacturing apparatus comprising a test circuit database that stores circuit data of a plurality of types of test circuits in association with a plurality of types of testing content; a definition information storing section that stores definition inf... | 05/26/2011 |
| 20110112678 | ADVANCED PROCESS CONTROL FOR NEW TAPEOUT PRODUCT The present disclosure provides a semiconductor manufacturing method. The method includes providing product data of a product, the product data including a sensitive product parameter; searching existing products according to the sensitive product parameter to identify ... | 05/12/2011 |
| 20110106286 | Generating A Power Model For An Electronic Device An apparatus that generates a power model for an electronic device, an apparatus that operates in accordance with a generated power model, and methods for generating a power for an electronic device are disclosed. In a particular embodiment, a method of generating a pow... | 05/05/2011 |
| 20110097903 | METHOD, APPARATUS AND PROGRAM FOR MANUFACTURING SILICON STRUCTURE A method for manufacturing a silicon structure according to the present invention includes, in a so-called dry-etching process wherein gas-switching is employed, the steps of: etching a portion in the silicon region at a highest etching rate under a high-rate etching co... | 04/28/2011 |
| 20110098838 | SYSTEM AND METHOD FOR CORRECTING SYSTEMATIC PARAMETRIC VARIATIONS ON INTEGRATED CIRCUIT CHIPS IN ORDER TO MINIMIZE CIRCUIT LIMITED YIELD LOSS Disclosed are a system and a method of correcting systematic, design-based, parametric variations on integrated circuit chips to minimize circuit limited yield loss. Processing information and a map of a chip are stored. The processing information can indicate an impact... | 04/28/2011 |
| 20110087359 | INTEGRATED CIRCUITS MODELING MANUFACTURING PROCEDURE AND MANUFACTURING SYSTEM UTILIZING THE SAME An ICs modeling manufacturing procedure is disclosed. A first pattern is printed on a first surface of a printed circuit board (PCB). The first pattern includes a first barcode and a plurality of production codes. A plurality of elements are disposed on the first surfac... | 04/14/2011 |
| 20110079923 | Vertically Stackable Dies Having Chip Identifier Structures A vertically stackable die having a chip identifier structure is disclosed. In a particular embodiment, a semiconductor device is disclosed that includes a die comprising a first through silicon via to communicate a chip identifier and other data. The semiconductor devi... | 04/07/2011 |
