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| Application No. | Application Title | Issue Date |
| 20120052600 | MANUFACTURING METHOD AND APPARATUS FOR SEMICONDUCTOR DEVICE A manufacturing method for a semiconductor device, comprising: performing first processing on a plurality of wafers in a first processing order in a first processing apparatus; obtaining a processed amount with respect to each of the plurality of wafers in the first pro... | 03/01/2012 |
| 20120028377 | USING OPTICAL METROLOGY FOR WITHIN WAFER FEED FORWARD PROCESS CONTROL A method of controlling the polishing of a substrate includes polishing a substrate on a first platen using a first set of parameters, obtaining first and second sequences of measured spectra from first and second regions of the substrate with an in-situ optical monitor... | 02/02/2012 |
| 20120009690 | IN-SITU SPECTROMETRY The present disclosure provides a system for in-situ spectrometry. The system includes a wafer-cleaning machine that cleans a surface of a semiconductor wafer using a cleaning solution. The system also includes a spectrometry machine that is coupled to the wafer-cleanin... | 01/12/2012 |
| 20120003759 | ENDPOINT CONTROL DURING CHEMICAL MECHANICAL POLISHING BY DETECTING INTERFACE BETWEEN DIFFERENT LAYERS THROUGH SELECTIVITY CHANGE Embodiments described herein relate to methods of detecting an endpoint for a target substrate during chemical mechanical polishing process. In one embodiment, the method includes polishing one or more target substrates at a first film removal rate to provide reference ... | 01/05/2012 |
| 20110318849 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE The semiconductor device of the present invention includes a first insulating film on a substrate having a first region and a second region, a light shielding film formed in the first region and an interconnect film formed in the second region in the first insulating fi... | 12/29/2011 |
| 20110275168 | SINGLE STEP CMP FOR POLISHING THREE OR MORE LAYER FILM STACKS A one-step CMP process for polishing three or more layer film stacks on a wafer having a multilayer film stack thereon including a silicon nitride (SiNx) layer on its semiconductor surface, and a silicon oxide layer on the SiNx layer, wherein trench access vias extend t... | 11/10/2011 |
| 20110256644 | MASKS FOR MICROLITHOGRAPHY AND METHODS OF MAKING AND USING SUCH MASKS Masks for microlithography apparatus, methods for making such masks, and methods for exposing photosensitive materials to form arrays of microfeatures on semiconductor wafers using such masks. In one embodiment, a method of making a mask comprises forming a mask layer o... | 10/20/2011 |
| 20110212548 | METHOD FOR SEMICONDUCTOR GATE HARDMASK REMOVAL AND DECOUPLING OF IMPLANTS A method is provided for fabricating a semiconductor device having implanted source/drain regions and a gate region, the gate region having been masked by the gate hardmask during source/drain implantation, the gate region having a polysilicon gate layered on a metal la... | 09/01/2011 |
| 20110195528 | POLISHING SYSTEM WITH IN-LINE AND IN-SITU METROLOGY A computer-implemented method for process control in chemical mechanical polishing in which an initial pre-polishing thickness of a substrate is measured at a metrology station, a parameter of an endpoint algorithm is determined from the initial thickness of the substra... | 08/11/2011 |
| 20110183444 | METHOD FOR ELECTRON BEAM INDUCED ETCHING The invention relates to a method for electron beam induced etching of a material (100, 200) with the method steps providing at least one etching gas at a position of the material (100, 200) at which an electron beam impacts on the material (100, 200 | 07/28/2011 |
| 20110151594 | METHOD AND SYSTEM FOR CONTROLLED ISOTROPIC ETCHING ON A PLURALITY OF ETCH SYSTEMS A method for forming identical isotropic etch patterns in an etch system is disclosed. The method comprises providing a wafer paddle, a wafer, a plurality of identical etch systems, utilizing identical etch recipes within each of the plurality of etch systems, providing... | 06/23/2011 |
| 20110014726 | METHOD OF FORMING SHALLOW TRENCH ISOLATION STRUCTURE A method for forming a shallow trench isolation (STI) structure with a predetermined target height is provided. A substrate having a pad oxide layer formed on the substrate is provided. A nitride-containing layer with a thickness is formed on the pad oxide. A STI struct... | 01/20/2011 |
| 20100216259 | WET PROCESSING SYSTEM, WET PROCESSING METHOD AND STORAGE MEDIUM A wet processing system detects a globule of a process solution in a drippy or dripping state from the tip of any one of process solution pouring nozzles being moved to a pouring position for pouring the process solution onto a substrate by obtaining image data on the p... | 08/26/2010 |
| 20100210041 | MULTI-ZONE TEMPERATURE CONTROL FOR SEMICONDUCTOR WAFER An apparatus includes a process chamber configured to perform an ion implantation process. A cooling platen or electrostatic chuck is provided within the process chamber. The cooling platen or electrostatic chuck is configured to support a semiconductor wafer. The cooli... | 08/19/2010 |
| 20100195684 | PHOTOELECTROCHEMICAL ETCHING FOR LASER FACETS A method for fabricating a semiconductor laser device, by etching facets using a photoelectrochemical (PEC) etch, so that the facets are sufficiently smooth to support optical modes within a cavity bounded by the facets.... | 08/05/2010 |
| 20100164113 | METHOD FOR FORMING COPPER WIRING IN SEMICONDUCTOR DEVICE A method for forming copper wirings in a semiconductor device may include depositing a lower insulating film over a semiconductor substrate; forming vias in the lower insulating film; depositing tungsten over the entire surface of upper portion of the lower insulating f... | 07/01/2010 |
| 20100129939 | USING OPTICAL METROLOGY FOR WITHIN WAFER FEED FORWARD PROCESS CONTROL A method of controlling the polishing of a substrate includes polishing a substrate on a first platen using a first set of parameters, obtaining first and second sequences of measured spectra from first and second regions of the substrate with an in-situ optical monitor... | 05/27/2010 |
| 20100029020 | SUBSTRATE PROCESSING CONTROL METHOD AND STORAGE MEDIUM In a substrate processing control method, a first process acquires a first-reflectance-spectrum of a beam reflected from the first-fine-structure and a second-reflectance-spectrum of a beam reflected from the second-fine-structure for each of varying-pattern-dimensions ... | 02/04/2010 |
| 20090311808 | METHOD FOR PRODUCING SEMICONDUCTOR WAFER A semiconductor wafer is produced by a method comprising a slicing step, an one-side polishing step and a chemical treating step, in which the kerf loss is reduced and the flatness is improved.... | 12/17/2009 |
| 20090305439 | METHOD FOR CORRECTING MASK PATTERN AND METHOD FOR MANUFACTURING ACCELERATION SENSOR AND ANGULAR VELOCITY SENSOR BY USING THE METHOD FOR CORRECTING THE MASK PATTERN A method for correcting a mask pattern used for dry-etching an object with higher accuracy, and for manufacturing an acceleration sensor and an angular velocity sensor. The object is first etched by a dry-etching process using an uncorrected reference mask pattern. Then... | 12/10/2009 |
| 20090275200 | TECHNIQUE FOR REDUCING TOPOGRAPHY-RELATED IRREGULARITIES DURING THE PATTERNING OF A DIELECTRIC MATERIAL IN A CONTACT LEVEL OF CLOSELY SPACED TRANSISTORS In a dual stress liner approach, the surface conditions after the patterning of a first stress-inducing layer may be enhanced by appropriately designing an etch sequence for substantially completely removing an etch stop material, which may be used for the patterning of... | 11/05/2009 |
| 20090239314 | Methods of Manufacturing a Semiconductor Device Methods of manufacturing a semiconductor device and an apparatus for the manufacturing of semiconductor devices are provided. An embodiment regards providing a process which changes the volume of at least one layer of a semiconductor substrate or of at least one layer d... | 09/24/2009 |
| 20090227047 | METHOD AND APPARATUS FOR THINNING A SUBSTRATE A method is provided for controlling substrate thickness. At least one etchant is dispensed from at least one dispenser to a plurality of different locations on a surface of a spinning substrate to perform etching. A thickness of the spinning substrate is monitored at t... | 09/10/2009 |
| 20090206450 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE OBTAINED HEREWITH, AND SLURRY SUITABLE FOR USE IN SUCH A METHOD The invention relates to a method of manufacturing a semiconductor device (10) with a substrate (11) and a semiconductor body (2) which is provided with at least one semiconductor element and the surface of which is provided with an aluminum layer (... | 08/20/2009 |
| 20090197353 | METHOD OF MANUFACTURING MATERIAL TO BE ETCHED A method is provided, of manufacturing a material to be etched that can more preferably prevent a region to be etched from remaining as an un-etched region and reduce deviation of etched/un-etched regions. Patterning (a method of manufactur... | 08/06/2009 |
| 20090179307 | INTEGRATED CIRCUIT SYSTEM EMPLOYING FEED-FORWARD CONTROL An integrated circuit system that includes: providing a substrate and a material layer; measuring a parameter of the material layer; and correlating the thickness of an anti-reflective layer to the measured parameter of the material layer for critical dimension control.... | 07/16/2009 |
| 20090176320 | METHOD FOR FABRICATION OF FLOATING GATE IN SEMICONDUCTOR DEVICE A method for manufacturing a floating gate includes: forming a tunnel oxide film on a semiconductor substrate; forming a polysilicon layer on a surface of the tunnel oxide film; forming a photosensitive film pattern on a surface of the polysilicon layer; depositing a by... | 07/09/2009 |
| 20090162951 | Enhanced Endpoint Detection In Non-Volatile Memory Fabrication Processes A method of fabricating non-volatile memory is provided for memory cells employing a charge storage element with multiple charge storage regions. A first charge storage layer is formed over a tunnel dielectric layer at both a memory array region and an endpoint region o... | 06/25/2009 |
| 20090159937 | Simple Scatterometry Structure for Si Recess Etch Control Dimensions of structures in integrated circuits are shrinking with each new fabrication technology generation. Maintaining control of profiles of structures in transistors and interconnects is becoming more important to sustaining profitable integrated circuit productio... | 06/25/2009 |
| 20090142859 | PLASMA CONTROL USING DUAL CATHODE FREQUENCY MIXING Methods for processing a substrate in a processing chamber using dual RF frequencies are provided herein. In some embodiments, a method of processing a substrate includes forming a plasma of a polymer forming chemistry to etch a feature into a substrate disposed on a su... | 06/04/2009 |
| 20090127722 | Method for Processing a Spacer Structure, Method of Manufacturing an Integrated Circuit, Semiconductor Device and Intermediate Structure with at Least One Spacer Structure Method for processing at least one spacer structure in a manufacturing process of a semiconductor device, wherein the at least one spacer structure is subjected to at least one etch process step with an isotropic component and the spacer structure comprises at least one... | 05/21/2009 |
| 20090087929 | METHOD AND SYSTEM FOR IMPROVING WET CHEMICAL BATH PROCESS STABILITY AND PRODUCTIVITY IN SEMICONDUCTOR MANUFACTURING A chemical processing bath and system used in semiconductor manufacturing utilizes a dynamic spiking model that essentially constantly monitors chemical concentration in the processing bath and adds fresh chemical on a regular basis to maintain chemical concentrations a... | 04/02/2009 |
| 20090068767 | TUNING VIA FACET WITH MINIMAL RIE LAG A method for designing an etch recipe is provided. An etch is performed, comprising providing an etch gas with a set halogen to carbon ratio, forming a plasma from the etch gas, and etching trenches over via. Via faceting is measured. The halogen to carbon ratio is rese... | 03/12/2009 |
| 20090053835 | VACUUM APPARATUS INCLUDING A PARTICLE MONITORING UNIT, PARTICLE MONITORING METHOD AND PROGRAM, AND WINDOW MEMBER FOR USE IN THE PARTICLE MONITORING A semiconductor manufacturing apparatus includes a processing chamber for performing a manufacturing processing on a wafer. A gas supply line for introducing a purge gas is connected to an upper portion of the processing chamber, a valve being installed on the gas suppl... | 02/26/2009 |
| 20090020849 | ELECTRONIC DEVICE INCLUDING A CAPACITOR AND A PROCESS OF FORMING THE SAME An electronic device can include electronic components and an insulating layer overlying the electronic components. The electronic device can also include a capacitor overlying the insulating layer, wherein the capacitor includes a first electrode and a second electrode... | 01/22/2009 |
| 20080305564 | MANUFACTURING APPARATUS FOR SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE A manufacturing apparatus for a semiconductor device, treating a SiN film formed on a wafer with phosphoric acid solution, including a processing bath to store phosphoric acid solution provided for treatment of the wafer, a control unit for calculating integrated SiN et... | 12/11/2008 |
| 20080305563 | Method and system for controlling copper chemical mechanical polish uniformity A system and method for controlling resistivity uniformity in a Copper trench structure by controlling the CMP process is provided. A preferred embodiment comprises a system and a method in which a plurality of CMP process recipes may be created comprising at least a sl... | 12/11/2008 |
| 20080299681 | MULTI-STEP DEPOSITION CONTROL For providing control of two-step or a multi-step deposition process, a method and a corresponding deposition system is provided comprising providing a deposition process having at least two sub-processes employing different sets of process parameters, wherein each set ... | 12/04/2008 |
| 20080295962 | METHOD AND SYSTEM FOR MASK HANDLING IN HIGH PRODUCTIVITY CHAMBER A structure for independently supporting a wafer and a mask in a processing chamber is provided. The structure includes a set of extensions for supporting the wafer and a set of extensions supporting the mask. The set of extensions for the wafer and the set of extension... | 12/04/2008 |
| 20080299682 | METHOD FOR REMOVING POLY SILICON Methods for removing poly silicon. In one example embodiment, a method for removing poly silicon that is formed on a silicon wafer includes the steps of growing the poly silicon as a silicon oxide through a thermal oxidation process and removing the silicon oxide using ... | 12/04/2008 |
