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| Application No. | Application Title | Issue Date |
| 20120126346 | METHOD FOR CREATING A MICROMECHANICAL MEMBRANE STRUCTURE AND MEMS COMPONENT In a method for manufacturing a micromechanical membrane structure, a doped area is created in the front side of a silicon substrate, the depth of which doped area corresponds to the intended membrane thickness, and the lateral extent of which doped area covers at least... | 05/24/2012 |
| 20120003835 | METHOD OF ETCHING SACRIFICIAL LAYER An exemplary method of etching sacrificial layer includes steps of: providing a substrate formed with a sacrificial layer and defined with a first region and a second region, the sacrificial layer disposed in both the first and second regions; forming a hard mask coveri... | 01/05/2012 |
| 20110275211 | Methods of Etching Nanodots, Methods of Removing Nanodots From Substrates, Methods of Fabricating Integrated Circuit Devices, Methods of Etching a Layer Comprising a Late Transition Metal, and Methods of Removing a Layer Comprising a Late Transition Metal From a Substrate Embodiments of the invention include methods of etching nanodots, to methods of removing nanodots from substrates, and to methods of fabricating integrated circuit devices. In one embodiment, a method of etching nanodots that include a late transition metal includes exp... | 11/10/2011 |
| 20110189858 | METHOD FOR REDUCING PATTERN COLLAPSE IN HIGH ASPECT RATIO NANOSTRUCTURES A method is provided for treating the surface of high aspect ratio nanostructures to help protect the delicate nanostructures during some of the rigorous processing involved in fabrication of semiconductor devices. A wafer containing high aspect ratio nanostructures is ... | 08/04/2011 |
| 20110183522 | METHOD AND APPARATUS FOR PATTERN COLLAPSE FREE WET PROCESSING OF SEMICONDUCTOR DEVICES A method is provided for processing a wafer used in fabricating semiconductor devices. The method can comprise forming high-aspect ratio features on the wafer, which is followed by wet processing and drying. During drying, pattern collapse can occur. This pattern collap... | 07/28/2011 |
| 20110177692 | Barrier Layer Removal Method and Apparatus This invention relates to a method and apparatus by integrating semiconductor manufacturing processes of stress free electrochemical copper polishing (SFP), removal of the Tantalum oxide or Titanium oxide formed during SFP process and XeF2 gas phase etching b... | 07/21/2011 |
| 20110111600 | PROCESSING METHOD FOR SOI SUBSTRATE A method of processing a SOI substrate to form a groove in the SOI substrate in which a silicon layer is stacked on both sides of an oxide layer is disclosed. In accordance with an embodiment of the present invention, the method includes dividing a portion of the silico... | 05/12/2011 |
| 20110049649 | INTEGRATED CIRCUIT SWITCHES, DESIGN STRUCTURE AND METHODS OF FABRICATING THE SAME Integrated MEMS switches, design structures and methods of fabricating such switches are provided. The method includes forming at least one tab of sacrificial material on a side of a switching device which is embedded in the sacrificial material. The method further incl... | 03/03/2011 |
| 20110049554 | PACKAGE BASE STRUCTURE AND MANUFACTURING METHOD THEREOF A package base structure for packaging a light-emitting element and a related manufacturing process are provided. The package base structure includes a semiconductor substrate having a top surface, a receiving space in the top surface and defined by slant surfaces, and ... | 03/03/2011 |
| 20100264519 | GATE TRIM PROCESS USING EITHER WET ETCH OR DRY ETCH APPRAOCH TO TARGET CD FOR SELECTED TRANSISTORS Disclosed are methods and devices for targeting CD of selected transistors in a semiconductor device. Varying CD is done by forming hard mask lines in a hard mask layer that have varying amounts of spacer material associated therewith. Hard mask lines corresponding to s... | 10/21/2010 |
| 20100248485 | METHOD FOR DIELECTRIC MATERIAL REMOVAL BETWEEN CONDUCTIVE LINES A method of removing carbon doped silicon oxide between metal contacts is provided. A layer of the carbon doped silicon oxide is converted to a layer of silicon oxide by removing the carbon dopant. The converted layer of silicon oxide is selectively wet etched with resp... | 09/30/2010 |
| 20100233882 | SINGLE SILICON-ON-INSULATOR (SOI) WAFER ACCELEROMETER FABRICATION Methods for creating at least one micro-electromechanical (MEMS) structure in a silicon-on-insulator (SOI) wafer. The SOI wafer with an extra layer of oxide is etched according to a predefined pattern. A layer of oxide is deposited over exposed surfaces. An etchant sele... | 09/16/2010 |
| 20100173498 | TRIM PROCESS FOR CRITICAL DIMENSION CONTROL FOR INTEGRATED CIRCUITS Methods of etching substrates employing a trim process for critical dimension control for integrated circuits are disclosed. In one embodiment, the method of etching includes providing a first hard mask layer over a target layer; providing a second hard mask layer over ... | 07/08/2010 |
| 20100144156 | METHOD TO INTEGRATE MICRO ELECTRO MECHANICAL SYSTEM AND CMOS IMAGE SENSOR A method to integrate a micro electro mechanical system and a CMOS image sensor is disclosed. First a substrate is provided. The substrate includes a micro electro mechanical system (MEMS) region and a CMOS image sensor (CIS) region. The micro electro mechanical system ... | 06/10/2010 |
| 20100120256 | METHOD FOR REMOVING ETCHING RESIDUES FROM SEMICONDUCTOR COMPONENTS A method for cleaning structured surfaces of semiconductor components to remove photoresist and etching residues after the etching of the surface, comprising: a) removal of the photoresist, b) treatment of the surface with an acidic aqueous solution comprising one or mo... | 05/13/2010 |
| 20100120255 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD A semiconductor device manufacturing method includes: forming a core pattern on a foundation film, the core pattern containing a material generating acid by light exposure; selectively exposing part of the core pattern except an longitudinal end portion; supplying a mas... | 05/13/2010 |
| 20100111802 | METHOD OF MANUFACTURING SILICON SINGLE CRYSTAL, SILICON SINGLE CRYSTAL INGOT, AND SILICON WAFER By determining a control direction of a pulling-up velocity without using a position or a width of an OSF region as an index, a subsequent pulling-up velocity profile is fed back and adjusted. A silicon single crystal ingot that does not include a COP and a dislocation ... | 05/06/2010 |
| 20100105211 | NANO-CRYSTAL ETCH PROCESS A method for selectively removing nano-crystals on an insulating layer. The method includes providing an insulating layer with nano-crystals thereon; exposing the nano-crystals to a high density plasma comprising a source of free radical chlorine, ionic chlorine, or bot... | 04/29/2010 |
| 20100093177 | METHOD OF CLEANING SEMICONDUCTOR WAFER AND SEMICONDUCTOR WAFER A silicon wafer surface other than a defect is oxidized by ozone to form a silicon oxide film. A hydrofluoric acid is sprayed and subsequently a cleaning gas is sprayed onto the surface of the silicon wafer.... | 04/15/2010 |
| 20100055916 | METHOD FOR DECAPSULATING PACKAGE A method for decapsulating a package is provided. The method comprises steps of providing a package having a chip therein, wherein the chip has an active surface and a rear surface. Further, the package further comprises a heat sink, a plurality of solder bumps, a subst... | 03/04/2010 |
| 20100055915 | Processing apparatus, processing method, and plasma source [Problems] A processing apparatus and a processing method that shorten a lead time and are more reliable than before in respect of the processing performance are provided. [Means for Solving Problems] The processing apparatus has a chamber,... | 03/04/2010 |
| 20100041236 | NOVEL METHOD TO INTEGRATE GATE ETCHING AS ALL-IN-ONE PROCESS FOR HIGH K METAL GATE The present disclosure provides a method for making metal gate stacks of a semiconductor device. The method includes applying a first dry etching process to a semiconductor substrate in an etch chamber through openings of a patterned mask layer defining gate regions, re... | 02/18/2010 |
| 20100041237 | METHOD FOR FORMING A FINE PATTERN USING ISOTROPIC ETCHING A method for forming a fine pattern using isotropic etching, includes the steps of forming an etching layer on a semiconductor substrate, and coating a photoresist layer on the etching layer, performing a lithography process with respect to the etching layer coated with... | 02/18/2010 |
| 20090233447 | CONTROL WAFER RECLAMATION PROCESS A method of recycling a control wafer having a dielectric layer deposited thereon involves removing most of the dielectric layer by plasma etching leaving a residual film of the dielectric and then removing the residual dielectric film by a wet etching process. The comb... | 09/17/2009 |
| 20090233389 | METHOD FOR MANUFACTURING THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING DISPLAY DEVICE A method for manufacturing a thin film transistor and a display device using a small number of masks is provided. A conductive film is formed, a thin-film stack body having a pattern is formed over the conductive film, an opening portion is formed in the thin-film stack... | 09/17/2009 |
| 20090223561 | METHOD OF ETCHING ASYMMETRIC WAFER, SOLAR CELL INCLUDING THE ASYMMETRICALLY ETCHED WAFER, AND METHOD OF MANUFACTURING THE SAME With the present invention, two wafers for a solar cell only whose light receiving surfaces are selectively etched can be simultaneously obtained by overlapping the two wafers and performing a single-sided etching or an asymmetric etching thereon. The present invention ... | 09/10/2009 |
| 20090221147 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE A method of fabricating a semiconductor device according to an embodiment includes: forming a core material on a workpiece material; forming a cover film to cover the upper and side surfaces of the core material; after forming the cover film, removing the core material;... | 09/03/2009 |
| 20090215156 | Method for Fabricating Nanogap and Nanogap Sensor The present invention relates to a method of fabricating a nanogap and a nanogap sensor, and to a nanogap and a nanogap sensor fabricated using the method. The present invention relates to a method of fabricating a nanogap and a nanogap sensor, which can be realized by ... | 08/27/2009 |
| 20090166871 | METAL LINE OF SEMICONDUCTOR DEVICE WITHOUT PRODUCTION OF HIGH RESISTANCE COMPOUND DUE TO METAL DIFFUSION AND METHOD FOR FORMING THE SAME A metal line includes a lower metal line formed on a semiconductor substrate. An insulation layer is formed on the semiconductor substrate having the lower metal line, and a metal line forming region exposing at least a portion of the lower metal line is defined in the ... | 07/02/2009 |
| 20090160028 | METHOD FOR FORMING GAPS IN MICROMECHANICAL DEVICE AND MICROMECHANICAL DEVICE An exemplary method for forming gaps in a micromechanical device includes providing a substrate. A first material layer is deposited over the substrate. A sacrificial layer is deposited over the first material layer. A second material layer is deposited over the sacrifi... | 06/25/2009 |
| 20090111205 | Method of seperating two material systems An embodiment of this invention discloses a method of separating two material systems, which comprises steps of providing a bulk sapphire; forming a nitride system on the bulk sapphire; forming at least two channels between the bulk sapphire and the nitride system; etch... | 04/30/2009 |
| 20090104767 | METHODS FOR FABRICATING RESIDUE-FREE CONTACT OPENINGS A two-step via cleaning process that removes metal polymer and oxide polymer residues from a via with substantially no damage to the via or underlying structures on a semiconductor substrate. The via is formed through a dielectric layer and a barrier layer that are disp... | 04/23/2009 |
| 20090087994 | METHOD OF FORMING FINE PATTERNS AND MANUFACTURING SEMICONDUCTOR LIGHT EMITTING DEVICE USING THE SAME A method of forming a fine pattern begins with providing a c-plane hexagonal semiconductor crystal. A mask having a predetermined pattern is formed on the semiconductor crystal. The semiconductor crystal is dry-etched by using the mask to form a first fine pattern on th... | 04/02/2009 |
| 20080293240 | MANUFACTURING METHOD OF A SILICON CARBIDE SEMICONDUCTOR DEVICE A manufacturing method for a silicon carbide semiconductor device is disclosed. It includes an etching method in which an Al film and Ni film are laid on an SiC wafer in this order and wet-etched, whereby a two-layer etching mask is formed in which Ni film portions over... | 11/27/2008 |
| 20080280450 | Method of two-step backside etching The present invention is related to a method of two-step backside-etching. First, a substrate with a plurality of hard masks is provided. Next, the back and the edge of the substrate are backside-etched to remove parts of the hard masks on the back and the edge of the s... | 11/13/2008 |
| 20080261403 | METHOD FOR OBTAINING HIGH-QUALITY BOUNDARY FOR SEMICONDUCTOR DEVICES FABRICATED ON A PARTITIONED SUBSTRATE One embodiment of the present invention provides a process for obtaining high-quality boundaries for individual multilayer structures which are fabricated on a trench-partitioned substrate. During operation, the process receives a trench-partitioned substrate wherein th... | 10/23/2008 |
| 20080242099 | Method for forming contact hole using dry and wet etching processes in semiconductor device A method for forming a contact hole in a semiconductor device includes forming an insulation layer over a substrate, forming a hard mask pattern over the insulation layer, forming a first contact hole by partially etching the insulation layer, forming a spacer on sidewa... | 10/02/2008 |
| 20080237686 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE A semiconductor device includes: a control gate electrode having a first layer of polycrystalline silicon. The first layer is formed by decreasing a thickness of a first film of doped polycrystalline silicon. The first layer retains a dopant activation ratio of the firs... | 10/02/2008 |
| 20080224238 | ADVANCED HIGH-k GATE STACK PATTERNING AND STRUCTURE CONTAINING A PATTERNED HIGH-k GATE STACK An advanced method of patterning a gate stack including a high-k gate dielectric that is capped with a high-k gate dielectric capping layer such as, for example, a rare earth metal (or rare earth like)-containing layer is provided. In particular, the present invention p... | 09/18/2008 |
| 20080220614 | METHOD FOR MANUFACTURING IMAGE SENSOR DEVICE The invention is directed to a method for manufacturing an image sensor device. The method comprises steps of forming a photodiode and a transistor on a substrate. A salicide block is formed over a photo-sensing region of the photodiode. An interconnects processes is pe... | 09/11/2008 |
