Quotables
"To place a man in a multi-stage rocket and project him into the controlling gravitational field of the moon where the passengers can make scientific observations, perhaps land alive, and then return to earth--all that constitutes a wild dream worthy of Jules Verne. I am bold enough to say that such a man-made voyage will never occur regardless of all future advances."
Lee deForest, American radio pioneer ; 1957
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Application No. | Application Title | Issue Date |
| 20120049358 | Semiconductor Device and Semiconductor Process for Making the Same The present invention relates to a semiconductor device and a semiconductor process for making the same. The semiconductor device of the present invention includes a semiconductor substrate, at least one conductive via and at least one insulation ring. The semiconductor... | 03/01/2012 |
| 20120049884 | Crack Sensors for Semiconductor Devices Crack sensors for semiconductor devices, semiconductor devices, methods of manufacturing semiconductor devices, and methods of testing semiconductor devices are disclosed. In one embodiment, a crack sensor includes a conductive structure disposed proximate a perimeter o... | 03/01/2012 |
| 20120049343 | CONDUCTIVE CONNECTION STRUCTURE WITH STRESS REDUCTION ARRANGEMENT FOR A SEMICONDUCTOR DEVICE, AND RELATED FABRICATION METHOD A semiconductor device disclosed herein includes a conductive connection structure having a stepped profile that serves as a stress relief feature. The conductive connection structure includes a stress buffer arrangement for a contact pad. The stress buffer arrangement ... | 03/01/2012 |
| 20120038052 | SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF A fabricating method of a semiconductor device is provided. Pillars are formed on a substrate. A first oxide layer is continuously formed on upper surfaces and side walls of the pillars by non-conformal liner atomic layer deposition. The first oxide layer continuously c... | 02/16/2012 |
| 20120032167 | SEMICONDUCTOR PACKAGE AND METHOD OF TESTING SAME A packaged integrated circuit includes a substrate having a wire layout pattern and a solder mask layer. An integrated circuit attached to a surface of the substrate is electrically connected to the wire layout pattern. An encapsulation material covers at least the inte... | 02/09/2012 |
| 20120018880 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF A semiconductor structure and a manufacture method thereof are disclosed. The semiconductor structure includes a semiconductor wafer having a plurality of semiconductor device dies, wherein each of the semiconductor device dies includes a die body, a metal wiring layer,... | 01/26/2012 |
| 20120018894 | NON-LITHOGRAPHIC FORMATION OF THREE-DIMENSIONAL CONDUCTIVE ELEMENTS A method of forming a conductive element on a substrate and the resulting assembly are provided. The method includes forming a groove in a sacrificial layer overlying a dielectric region disposed on a substrate. The groove preferably extends along a sloped surface of th... | 01/26/2012 |
| 20120015500 | Method of manufacturing wafer level package A method for manufacturing a wafer level package including: forming a redistribution line connected to a top surface of a die pad on a wafer with the die pad; additionally preparing a carrier film including a metal post with a concave central portion on one surface; bon... | 01/19/2012 |
| 20120012987 | METHODS OF FORMING SEMICONDUCTOR CHIP UNDERFILL ANCHORS Various semiconductor chips and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first opening in an insulating layer applied to a side of a semiconductor chip. The first opening does not extend throu... | 01/19/2012 |
| 20120009783 | Solder Bump With Inner Core Pillar in Semiconductor Package A flip chip semiconductor package has a substrate with a plurality of active devices. A contact pad is formed on the substrate in electrical contact with the plurality of active devices. A passivation layer, second barrier layer, and adhesion layer are formed between th... | 01/12/2012 |
| 20120007245 | Via and Method of Forming the Via with a Substantially Planar Top Surface that is Suitable for Carbon Nanotube Applications A via is formed on a wafer to lie within an opening in a non-conductive structure and make an electrical connection with an underlying conductive structure so that the entire top surface of the via is substantially planar, and lies substantially in the same plane as the... | 01/12/2012 |
| 20120009780 | WIRE BONDING ON REACTIVE METAL SURFACES OF A METALLIZATION OF A SEMICONDUCTOR DEVICE BY PROVIDING A PROTECTION LAYER In semiconductor devices having a copper-based metallization system, bond pads for wire bonding may be formed directly on copper surfaces, which may be covered by an appropriately designed protection layer to avoid unpredictable copper corrosion during the wire bond pro... | 01/12/2012 |
| 20120003832 | METHOD OF REDUCING EROSION OF A METAL CAP LAYER DURING VIA PATTERNING IN SEMICONDUCTOR DEVICES During the patterning of via openings in sophisticated metallization systems of semiconductor devices, the opening may extend through a conductive cap layer and an appropriate ion bombardment may be established to redistribute material of the underlying metal region to ... | 01/05/2012 |
| 20110318921 | Methods Of Forming An Interconnect Between A Substrate Bit Line Contact And A Bit Line In DRAM The invention includes methods of electrically interconnecting different elevation conductive structures, methods of forming capacitors, methods of forming an interconnect between a substrate bit line contact and a bit line in DRAM, and methods of forming DRAM memory ce... | 12/29/2011 |
| 20110316170 | Wiring Substrate, Semiconductor Device, and Method for Manufacturing Wiring Substrate A wiring substrate includes a wiring pattern in an uppermost layer that includes pads. A solder resist layer covers the wiring pattern. A recess exposes part of the wiring pattern from the solder resist layer to form pads. The solder resist layer includes a portion form... | 12/29/2011 |
| 20110309503 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF A semiconductor device comprises a semiconductor chip having a plurality of electrode pads; an insulation layer having one or more apertures which expose at least a part of the plurality of electrode pads respectively on the semiconductor chip; and a plurality of wires ... | 12/22/2011 |
| 20110306206 | Methods Of Forming Contact Openings And Methods Of Increasing Contact Area In Only One Of X and Y Axes In The Fabrication Of Integrated Circuitry A method of forming contact openings in the fabrication of integrated circuitry includes forming a mask which includes at least one of photoresist and amorphous carbon received over a plurality of spaced conductive line constructions. The conductive line constructions i... | 12/15/2011 |
| 20110294285 | PHOTO KEY AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING THE PHOTO KEY A photo key has a plurality of first regions spaced apart from one another on a semiconductor substrate, and a second region surrounding the first regions, and one of the first regions and the second region constitutes a plurality of photo key regions spaced apart from ... | 12/01/2011 |
| 20110294296 | Using edges of self-assembled monolayers to form narrow features The present invention provides a method for manufacturing a structure over a semiconductor substrate. To form a trench, a patterned layer is formed on a portion of a substrate such that the patterned layer forms a target area located adjacent an edge of the patterned la... | 12/01/2011 |
| 20110294290 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME A three-dimensional semiconductor memory device includes a stacked structure including a plurality of conductive patterns, an active pillar penetrating the stacked structure, and a data storage pattern between the active pillar and the conductive patterns, wherein the a... | 12/01/2011 |
| 20110285028 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME A semiconductor device has an insulating film, serving as low-porosity regions low in porosity, formed on a substrate and high-porosity regions higher in porosity than the low-porosity regions, and also includes copper interconnects formed to fill interconnect grooves i... | 11/24/2011 |
| 20110285015 | BUMP STRUCTURE AND FABRICATION METHOD THEREOF There is provided a bump structure for a semiconductor device, comprising a metal post formed on and electrically connected to an electrode pad on a substrate, a solder post formed on the top surface of the metal post, said solder post having the same horizontal width a... | 11/24/2011 |
| 20110266034 | Preventing breakage of long metal signal conductors on semiconductor substrates An apparatus includes a volume of insulator disposed over a top surface of a semiconductor substrate, a tube of soft dielectric, and a metal conductor. The insulator has a hardness of more than approximately three gigaPascals (gPa) and the soft dielectric has a hardness... | 11/03/2011 |
| 20110256713 | POLYHEDRAL OLIGOMERIC SILSESQUIOXANE BASED IMPRINT MATERIALS AND IMPRINT PROCESS USING POLYHEDRAL OLIGOMERIC SILSESQUIOXANE BASED IMPRINT MATERIALS A method of forming low dielectric contrast structures by imprinting a silsesquioxane based polymerizable composition. The imprinting composition including: one or more polyhedral silsesquioxane oligomers each having one or more polymerizable groups, wherein each of the... | 10/20/2011 |
| 20110254154 | ROUTING LAYER FOR MITIGATING STRESS IN A SEMICONDUCTOR DIE A routing layer for a semiconductor die is disclosed. The routing layer includes traces interconnecting integrated circuit bond-pads to UBMs. The routing layer is formed on a layer of dielectric material. The routing layer includes conductive traces arranged underneath ... | 10/20/2011 |
| 20110227232 | CRENULATED WIRING STRUCTURE AND METHOD FOR INTEGRATED CIRCUIT INTERCONNECTS A method for forming crenulated conductors and a device having crenulated conductors includes forming a hardmask layer on a dielectric layer, and patterning the hardmask layer. Trenches are etched in the dielectric layer using the hardmask layer such that the trenches h... | 09/22/2011 |
| 20110215482 | Semiconductor device The semiconductor device according to the present invention includes a semiconductor layer, an interlayer dielectric film formed on the semiconductor layer, a wire formed on the interlayer dielectric film with a metallic material to have a width of not more than 0.4 μm... | 09/08/2011 |
| 20110212616 | METALLIZATION SYSTEM OF A SEMICONDUCTOR DEVICE COMPRISING ROUNDED INTERCONNECTS FORMED BY HARD MASK ROUNDING In sophisticated metallization systems, vertical contacts and metal lines may be formed on the basis of a dual inlaid strategy, wherein an edge rounding or corner rounding may be applied to the trench hard mask prior to forming the via openings on the basis of a self-al... | 09/01/2011 |
| 20110203656 | Nanoscale High-Aspect-Ratio Metallic Structure and Method of Manufacturing Same Nanoscale high-aspect-ratio metallic structures and methods are presented. Such structures may form transparent electrode to enhance the performance of solar cells and light-emitting diodes. These structures can be used as infrared control filters because they reflect h... | 08/25/2011 |
| 20110208467 | CALIBRATION STANDARDS AND METHODS OF THEIR FABRICATION AND USE An embodiment of a calibration standard includes a substrate, a set of conductive structures fabricated on the substrate, and a conductive end structure fabricated on the substrate. The set of conductive structures include an inner conductive structure, a first outer co... | 08/25/2011 |
| 20110193085 | Methods of Forming Structures with a Focused ION Beam for Use in Atomic Force Probing and Structures for Use in Atomic Force Probing Methods for forming structures to use in atomic force probing of a conductive feature embedded in a dielectric layer and structures for use in atomic force probing. An insulator layer is formed on the dielectric layer such that the conductive feature is covered. A conta... | 08/11/2011 |
| 20110175193 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD A semiconductor device according to the present invention includes a semiconductor substrate, and an interlayer dielectric film, formed on the semiconductor substrate, having a multilayer structure of a compressive stress film and a tensile stress film.... | 07/21/2011 |
| 20110157526 | ELECTRODE CONTACT STRUCTURE, LIQUID CRYSTAL DISPLAY APPARATUS INCLUDING SAME, AND METHOD FOR MANUFACTURING ELECTRODE CONTACT STRUCTURE A water-repellent pattern (26) made from a water-repellent material is provided around a contact hole (20), and causes a polarizing layer (24) made from a water-soluble material to be separated from the contact hole (20). It is therefore poss... | 06/30/2011 |
| 20110159684 | SRAM CELL WITH T-SHAPED CONTACT An integrated circuit containing an array of SRAM cells with T-shaped contacts in the inverters, in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain c... | 06/30/2011 |
| 20110140288 | Systems and Methods Employing a Physically Asymmetric Semiconductor Device Having Symmetrical Electrical Behavior An integrated circuit device comprising a first elongate structure and a second elongate structure arranged parallel to each other and defining a space therebetween. The integrated circuit device also includes conductive structures distributed in the space between the f... | 06/16/2011 |
| 20110133311 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE The semiconductor device includes a capacitor including a plurality of interconnection layers stacked over each other, the plurality of interconnection layers each including a plurality of electrode patterns extended in a first direction, a plurality of via parts provid... | 06/09/2011 |
| 20110129975 | METHOD FOR FABRICATING SIDE CONTACT IN SEMICONDUCTOR DEVICE USING DOUBLE TRENCH PROCESS A method for fabricating a semiconductor device is provided, the method includes forming a double trench including a first trench and a second trench formed below the first trench and having surfaces covered with insulation layers, and removing portions of the insulatio... | 06/02/2011 |
| 20110108942 | METHOD FOR PRODUCING FIELD EFFECT TRANSISTORS WITH A BACK GATE AND SEMICONDUCTOR DEVICE The method for producing a field effect transistor on a substrate comprising a support layer, a sacrificial layer and a semi-conducting layer comprises forming an active area in the semi-conducting layer. The active area is delineated by a closed peripheral insulation p... | 05/12/2011 |
| 20110108994 | INTEGRATED CIRCUITS AND METHODS FOR FORMING THE INTEGRATED CIRCUITS A method for forming an integrated circuit includes forming a first dielectric layer over a gate electrode of a transistor. An etch-stop layer is formed over the first dielectric layer. An opening is formed through the first dielectric layer and the etch-stop layer, exp... | 05/12/2011 |
| 20110104894 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE A method for fabricating a semiconductor device includes etching a semiconductor substrate using a hard mask layer as a barrier to form a trench defining a plurality of active regions, forming a gap-fill layer to gap-fill a portion of the inside of the trench so that th... | 05/05/2011 |
