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| Application No. | Application Title | Issue Date |
| 20120126409 | SEED LAYERS FOR METALLIC INTERCONNECTS AND PRODUCTS A method is disclosed for depositing multiple seed layers for metallic interconnects over a substrate, the substrate includes a patterned insulating layer which comprises an opening surrounded by a field, said opening has sidewalls and top corners, and the method includ... | 05/24/2012 |
| 20110284996 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME In one embodiment, a semiconductor device includes a substrate, and a plurality of interconnects provided in the same interconnect layer above the substrate. The device further includes a plurality of insulators provided so as to be buried between the plurality of inter... | 11/24/2011 |
| 20090263964 | INTERCONNECTIONS FOR INTEGRATED CIRCUITS An interconnect connection structure having first and second interconnects and multiple connection elements that electrically connect the first interconnect to the second interconnect is described. The multiple connection elements are formed laterally in a lateral regio... | 10/22/2009 |
| 20080239792 | METAL SILICIDE ALLOY LOCAL INTERCONNECT A local interconnect is formed with a gate conductor line that has an exposed sidewall on an active area of a semiconductor substrate. The exposes sidewall comprises a silicon containing material that may form a silicide alloy upon silicidation. During a silicidation pr... | 10/02/2008 |
| 20080157342 | Package with a marking structure and method of the same The present invention provides a semiconductor device package with a metal marking structure comprising a substrate with a die receiving cavity formed within an upper surface of the substrate and a through hole structure formed there through, wherein a terminal pad is f... | 07/03/2008 |
| 20070259502 | Parasitic particle suppression in growth of III-V nitride films using MOCVD and HVPE A method of suppressing parasitic particle formation in a metal organic chemical vapor deposition process is described. The method may include providing a substrate to a reaction chamber, and introducing an organometallic precursor, a particle suppression compound and a... | 11/08/2007 |
| 20060234499 | Substrate processing method and substrate processing apparatus A substrate processing method forms a plated film which is thin and has a high flatness by covering the surface (outermost surface) of a substrate, excluding interior surfaces of recesses such as trenches, with a plating inhibiting material such as an SAM-forming molecu... | 10/19/2006 |
| 20060223308 | APPARATUS FOR MANUFACTURING A SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME An apparatus for manufacturing a semiconductor includes a polyhedral transfer chamber, a first process module for forming a gate dielectric layer by ALD, and a second process module for thermally treating the gate dielectric layer. The first process module is in communi... | 10/05/2006 |
| 20060216932 | Plasma pre-treating surfaces for atomic layer deposition Method and structures are provided for conformal lining of dual damascene structures in integrated circuits. Preferred embodiments are directed to providing conformal lining over openings formed in porous materials. Trenches are formed in, preferably, insulating layers.... | 09/28/2006 |
| 20060088997 | METHOD TO PRODUCE LOW STRENGTH TEMPORARY SOLDER JOINTS The present invention provides a method for producing a temporary chip carrier for semiconductor chip burn-in test and speed sorting. A multi-layered substrate or card, usually comprised of one of various materials is made by offsetting the conductor-filled vias or hole... | 04/27/2006 |
| 20050032352 | H2 plasma treatment Electronic devices are constructed by a method that includes forming a first conductive layer in an opening in a multilayer dielectric structure supported by a substrate, forming a core conductive layer on the first conductive layer, subjecting the core conductive layer... | 02/10/2005 |
| 20050003658 | Methods for forming via plugs An aerosol stream of particles of a conductive material is directed into a via of an integrated circuit device to deposit the conductive material within the via to form a via plug. ... | 01/06/2005 |
| 20050003659 | Transparent inter-metal dielectric stack for CMOS image sensors A transparent inter-metal dielectric utilized in a CMOS image sensor includes a flowlayer sandwiched between a base SiO2 layer and a cap SiO2 layer. The flowlayer is formed by reacting SiH4 and H2O2 using a shortene... | 01/06/2005 |
