Bizarre Patents
Cloaking System Using Optoelectronically Controlled Camouflage
A Cloaking System designed to operate in the visible light spectrum, utilizes optoelectronics and/or photonic components to conceal an object within it.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Application No. | Application Title | Issue Date |
| 20120003831 | Methods of Forming Nonvolatile Memory Devices Using Nonselective and Selective Etching Techniques to Define Vertically Stacked Word Lines Methods of forming nonvolatile memory devices include forming a stack of layers of different materials on a substrate. This stack includes a plurality of first layers of a first material and a plurality of second layers of a second material arranged in an alternating se... | 01/05/2012 |
| 20100320605 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME Provided are a semiconductor device and a method of fabricating the semiconductor memory device. A contact plug is formed by wet etching. An aspect ratio of SAC is decreased and SAC fail is reduced so that a process margin is secured. The semiconductor device includes a... | 12/23/2010 |
| 20100233875 | CONTACT FORMATION The present disclosure includes various method of contact embodiments. One such method embodiment includes creating a trench in an insulator stack material of a particular thickness and having a portion of the trench positioned between two of a number of gates. This met... | 09/16/2010 |
| 20100225003 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE OBTAINABLE WITH SUCH A METHOD A method for manufacturing a semiconductor device includes providing a patterned hard-mask layer. The hard-mask layer is provided on an exposed surface of one or more layers to be patterned of a semiconductor intermediate product. The hard-mask layer covers the exposed ... | 09/09/2010 |
| 20100171223 | Through-Silicon Via With Scalloped Sidewalls A semiconductor device having one or more through-silicon vias (TSVs) is provided. The TSVs are formed such that sidewalls of the TSVs have a scalloped surface. In an embodiment, the sidewalls of the TSVs are sloped wherein a top and bottom of the TSVs have different di... | 07/08/2010 |
| 20090096108 | STRUCTURE AND METHODS OF FORMING CONTACT STRUCTURES Methods and a structure. A method of forming contact structure includes depositing a silicide layer onto a substrate; depositing an electrically insulating layer over a first surface of the silicide layer; forming a via through the insulating layer extending to the firs... | 04/16/2009 |
| 20090017576 | Semiconductor Processing Methods Some embodiments include methods of forming semiconductor constructions in which a semiconductor material sidewall is along an opening, a protective organic material is over at least one semiconductor material surface, and the semiconductor material sidewall and protect... | 01/15/2009 |
| 20090014886 | DYNAMIC RANDOM ACCESS MEMORY WITH AN ELECTROSTATIC DISCHARGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME The invention provides a dynamic random access memory (DRAM) with an electrostatic discharge (ESD) region. The upper portion of the ESD plug is metal, and the lower portion of the ESD plug is polysilicon. This structure may improve the mechanical strength of the ESD reg... | 01/15/2009 |
| 20080217782 | METHOD FOR PREPARING 2-DIMENSIONAL SEMICONDUCTOR DEVICES FOR INTEGRATION IN A THIRD DIMENSION A method which is intended to facilitate and/or simplify the process of fabricating interlayer vias by selective modification of the FEOL film stack on a transfer wafer is provided. Specifically, the present invention provides a method in which two dimensional devices a... | 09/11/2008 |
| 20080220608 | MODIFIED VIA BOTTOM STRUCTURE FOR RELIABILITY ENHANCEMENT The present invention provides an interconnect structure that can be made in the BEOL which exhibits good mechanical contact during normal chip operations and does not fail during various reliability tests as compared with the conventional interconnect structures descri... | 09/11/2008 |
| 20080211106 | VIA/CONTACT AND DAMASCENE STRUCTURES AND MANUFACTURING METHODS THEREOF A method for forming a semiconductor structure includes forming a dielectric layer over a substrate. A first non-conductive barrier layer is formed over the dielectric layer. At least one opening is formed through the first non-conductive barrier layer and within the di... | 09/04/2008 |
| 20080179755 | STRUCTURE AND METHOD FOR CREATING RELIABLE DEEP VIA CONNECTIONS IN A SILICON CARRIER A process and structure for enabling the creation of reliable electrical through-via connections in a semiconductor substrate and a process for filling vias. Problems associated with under etch, over etch and flaring of deep Si RIE etched through-vias are mitigated, the... | 07/31/2008 |
| 20080182407 | METHOD OF FORMING VIAS IN A SEMICONDUCTOR DEVICE A via is formed in contact with a conductive line, whereby the via is offset from the conductive line so that the via extends beyond the conductive line. In accordance with a specific embodiment, a portion of the via contacts a sidewall of the conductive line.... | 07/31/2008 |
| 20080136038 | INTEGRATED CIRCUITS WITH CONDUCTIVE FEATURES IN THROUGH HOLES PASSING THROUGH OTHER CONDUCTIVE FEATURES AND THROUGH A SEMICONDUCTOR SUBSTRATE A backside contact pad is formed in an integrated circuit, possibly designed initially with just top side contact pads (150C), by forming an opening (220) through a top side contact pad (150C) and the semiconductor substrate (110). Conductive... | 06/12/2008 |
| 20080119042 | SYSTEMS AND METHODS FOR BACK END OF LINE PROCESSING OF SEMICONDUCTOR CIRCUITS A BEOL manufacturing process for forming a via process between two metal lines on a semiconductor wafer comprises depositing a portion of a first metal adhesion layer within a patterned via hole, followed by a cooling step. The cooling step is then followed by formation... | 05/22/2008 |
| 20080116582 | Interconnect Structures with Improved Electromigration Resistance and Methods for Forming Such Interconnect Structures Interconnect structures including liner layers that are non-planar with at least the adjacent insulating layer and at least one capping layer on conductive features embedded in the insulating layer. The interconnect structure includes an insulating layer of a dielectric... | 05/22/2008 |
| 20080102624 | Method of fabricating semiconductor device with recess gate A method of fabricating a semiconductor device includes forming a hard mask pattern over a substrate, wherein the hard mask pattern exposes a recess region, performing a first etching process on the exposed recess region to form a first recess having sidewalls and to fo... | 05/01/2008 |
| 20080088029 | SEMICONDUCTOR DEVICE HAVING CONTACT BARRIER AND METHOD OF MANUFACTURING THE SAME A semiconductor device having a contact barrier for insulating contacts with a large aspect ratio and having a fine pitch between adjacent conductive lines and a method of manufacturing the same are provided. The semiconductor device includes a buried contact formed in ... | 04/17/2008 |
| 20080003812 | METHOD OF MANUFACTURING SELF-ALIGNED CONTACT OPENINGS A method of manufacturing self-aligned contact openings is provided. A substrate having a number of device structures is provided and the top of the device structures is higher than the surface of the substrate. A first dielectric layer and a conductive layer are sequen... | 01/03/2008 |
| 20070218682 | SEMICONDUCTOR DEVICE Bit lines having first conductive patterns and bit line mask patterns are formed on a first insulating layer between capacitor contact regions of a substrate. An oxide second insulating layer is formed on the bit lines and contact patterns are formed to open storage nod... | 09/20/2007 |
| 20070099416 | Shrinking Contact Apertures Through LPD Oxide Sublithographic contact apertures through a dielectric are formed in a stack of dielectric, hardmask and oxide-containing seed layer. An initial aperture through the seed layer receives a deposition of oxide by liquid phase deposition, which adheres selectively to the e... | 05/03/2007 |
| 20070082484 | METHODS OF FABRICATING SEMICONDUCTOR DEVICE HAVING SLOPE AT LOWER SIDES OF INTERCONNECTION HOLE WITH ETCH-STOP LAYER Methods of manufacturing semiconductor devices having slopes at lower sides of an interconnection hole include an etch-stop layer and an interlayer dielectric layer sequentially formed on a semiconductor substrate having the lower conductive layer. Portions of the etch-... | 04/12/2007 |
| 20070072412 | PREVENTING DAMAGE TO INTERLEVEL DIELECTRIC Prevention of damage to an interlevel dielectric (ILD) is provided by forming an opening (e.g., trench) in the ILD, and sputtering a dielectric film onto a sidewall of the opening by overetching into a layer of the dielectric below or within the ILD during forming of th... | 03/29/2007 |
| 20070035025 | Damascene processing using dielectric barrier films Damascene processing is implemented with dielectric barrier films for improved step coverage and reduced contact resistance. Embodiments include the use of two different dielectric films to avoid misalignment problems. Embodiments further include dual damascene processi... | 02/15/2007 |
| 20070010085 | Semiconductor device and fabrication method thereof Semiconductor devices and methods for fabricating the same. The devices includes a substrate, a first etch stop layer, a dielectric layer, an opening, and an anti-diffusion layer. The first etch stop layer overlies the substrate. The dielectric layer overlies the first ... | 01/11/2007 |
| 20070007656 | Semiconductor device and methods thereof An insulation interlayer having first contact holes exposing first contact pads is formed on a semiconductor structure having the first and second contact pads. Conductive patterns connected to the first contact pads through the first contact holes are formed on the ins... | 01/11/2007 |
| 20070004196 | Method for forming storage node contact in semiconductor device using nitride-based hard mask A method for forming a storage node contact in a semiconductor device using a nitride-based hard mask is provided. The method includes: forming an inter-layer oxide layer on a substrate; forming a hard mask containing a nitride material on the inter-layer oxide layer; f... | 01/04/2007 |
| 20070004197 | Methods for creating electrophoretically insulated vias in semiconductive substrates Methods are provided for creating lined vias in semiconductor substrates. Using electrophoretic deposition techniques, micelles of a lining material are deposited on the wall of the via, reacting with the surface of the wall until the entire wall is covered by the linin... | 01/04/2007 |
| 20060292863 | PREVENTING DAMAGE TO METAL USING CLUSTERED PROCESSING AND AT LEAST PARTIALLY SACRIFICIAL ENCAPSULATION Methods are disclosed for metal encapsulation for preventing exposure of metal during semiconductor processing. In one embodiment, the method includes forming an opening in a structure exposing a metal surface in a bottom of the opening, where the opening forming step o... | 12/28/2006 |
| 20060284311 | METHOD OF MANUFACTURING SELF-ALIGNED CONTACT OPENINGS AND SEMICONDUCTOR DEVICE A method of manufacturing self-aligned contact openings is provided. A substrate having a plurality of device structures is provided and the top of the device structures is higher than the surface of the substrate. A first dielectric layer and a conductive layer are seq... | 12/21/2006 |
| 20060267201 | Technique for forming copper-containing lines embedded in a low-k dielectric by providing a stiffening layer By providing a stiffening layer at three sidewalls of a trench to be filled with a copper-containing metal, the reduced thermomechanical confinement of a low-k material may be compensated for, at least to a certain degree, thereby reducing electromigration effects and h... | 11/30/2006 |
| 20060264027 | Air gap interconnect structure and method thereof Methods for fabricating interconnect structures implementing air gaps therein is provided. In one embodiment, a semiconductor substrate with a first barrier layer formed thereon is provided. A first dielectric layer is formed above the barrier layer. The first dielectri... | 11/23/2006 |
| 20060252259 | Ion implantation of spin on glass materials A spin on glass SOG layer 30 is formed, then a PECVD barrier layer 40 over the SOG layer. Holes 50 in the SOG layer for vias are formed with a wine glass profile, so that in a peripheral region around the periphery of the holes, the barrier layer is... | 11/09/2006 |
| 20060240664 | Method of manufacturing multi-layered substrate A method of manufacturing a multi-layered substrate includes providing an electronic component on a surface of a substrate so that a terminal of the electronic component faces upward. The method also includes providing a first insulation pattern on the surface so as to ... | 10/26/2006 |
| 20060231900 | Semiconductor device having fine contacts and method of fabricating the same A semiconductor device has a structure of contacts whose size and pitch are finer that those that can be produced under the resolution provided by conventional photolithography. The contact structure includes a semiconductor substrate, an interlayer insulating layer dis... | 10/19/2006 |
| 20060228852 | Method of forming contact plugs A method of forming cell bitline contact plugs is disclosed in the present invention. After providing a semiconductor substrate with a first region and a second region, cell bitline contacts are formed at the first region. After forming bitline pattern openings at the s... | 10/12/2006 |
| 20060216931 | Method for reducing dielectric overetch when making contact to conductive features In a first preferred embodiment of the present invention, conductive features are formed on a first dielectric etch stop layer, and a second dielectric material is deposited over and between the conductive features. A via etch to the conductive features which is selecti... | 09/28/2006 |
| 20060211239 | METHODS OF FABRICATING DOUBLE-SIDED HEMISPHERICAL SILICON GRAIN ELECTRODES AND CAPACITOR MODULES Methods are provided for robust and cost effective techniques to fabricate a semiconductor device having double-sided hemispherical silicon grain (HSG) electrodes for container capacitors. In an embodiment, this is accomplished by forming a layer of hemispherical silico... | 09/21/2006 |
| 20060205208 | Method for manufacturing a semiconductor device and method for etching the same A method for manufacturing a semiconductor device with a dual damascene structure is comprising the steps of preparing a semiconductor substrate, forming a first wiring layer over said semiconductor substrate, forming an inorganic insulating film over said first wiring ... | 09/14/2006 |
| 20060189128 | Method of forming a conductive line and a method of forming a conductive contact adjacent to and insulated from a conductive line This invention includes methods of forming conductive lines, and methods of forming conductive contacts adjacent conductive lines. In one implementation, a method of forming a conductive line includes forming a conductive line within an elongated trench within first ins... | 08/24/2006 |
