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| Application No. | Application Title | Issue Date |
| 20110059607 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD A method for making a semiconductor device including at least three interconnection layers sequentially stacked without intervention of a via layer. At least one of the interconnection layers includes an interconnection and a via which connects interconnections provided... | 03/10/2011 |
| 20100255674 | METHOD OF FORMING CONTACT STRUCTURE Provided is a method of forming a contact structure. The method includes forming a conductive pattern on a substrate. An interlayer insulating layer covering the conductive pattern is formed. The interlayer insulating layer is patterned to form an opening partially expo... | 10/07/2010 |
| 20100176514 | INTERCONNECT WITH RECESSED DIELECTRIC ADJACENT A NOBLE METAL CAP The invention comprises a copper interconnect structure that includes a noble metal cap with dielectric immediately adjacent the copper/noble metal cap interface recessed from the noble metal cap.... | 07/15/2010 |
| 20100155949 | LOW COST PROCESS FLOW FOR FABRICATION OF METAL CAPPING LAYER OVER COPPER INTERCONNECTS Semiconductor devices and methods are disclosed for improving electrical connections to integrated circuits. A process flow and device with a dual/single damascene interconnect structure overlying an existing interconnect structure in a semiconductor wafer is provided. ... | 06/24/2010 |
| 20100013104 | INTEGRATED CIRCUIT HARD MASK PROCESSING SYSTEM An integrated circuit processing system is provided including a substrate having an integrated circuit; an interconnect layer over the integrated circuit; a low-K dielectric layer over the interconnect layer; a hard mask layer over the low-K dielectric layer; a via open... | 01/21/2010 |
| 20090311829 | Performing Die-to-Wafer Stacking by Filling Gaps Between Dies An integrated circuit structure includes a bottom semiconductor chip; a top die bonded onto the bottom semiconductor chip; a protecting material encircling the bottom die and on the bottom semiconductor chip; and a planar dielectric layer over the top die and the protec... | 12/17/2009 |
| 20090184421 | SEMICONDUCTOR DEVICE WITH HIGH RELIABILITY AND MANUFACTURING METHOD THEREOF A semiconductor device is provided, which includes a substrate, an insulator film formed over the substrate, and plural metal wirings with different widths containing copper as a main component and an impurity which is different from copper. The plural metal wirings inc... | 07/23/2009 |
| 20090152722 | Synergy Effect of Alloying Materials in Interconnect Structures A method of forming an integrated circuit structure, the method includes providing a semiconductor substrate; forming a dielectric layer over the semiconductor substrate; forming an opening in the dielectric layer; forming a seed layer in the opening; forming a copper l... | 06/18/2009 |
| 20090152724 | IC INTERCONNECT FOR HIGH CURRENT IC interconnect for high current device, design structure thereof and method are disclosed. One embodiment of the IC interconnect includes a first via positioned in a dielectric and coupled to a high current device at one end; a buffer metal segment positioned in a diel... | 06/18/2009 |
| 20090146309 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME A semiconductor device has a first insulating film formed over a semiconductor substrate, a first opening formed in the first insulating film, a first manganese oxide film formed along an inner wall of the first opening, a first copper wiring embedded in the first openi... | 06/11/2009 |
| 20090142917 | METHOD FOR FABRICATING METAL LINE OF SEMICONDUCTOR DEVICE Methods for fabricating a metal line of a semiconductor device are disclosed. In a disclosed example, the method includes a first step of forming a passivation film on a semiconductor substrate having a semiconductor device, a second step of forming contact holes in the... | 06/04/2009 |
| 20090087980 | METHODS OF LOW-K DIELECTRIC AND METAL PROCESS INTEGRATION An integrated process for forming metallization layers for electronic devices that use damascene structures that include low-k dielectric and metal. According to one embodiment of the present invention, the integrated process includes planarizing a gapfill metal in low-... | 04/02/2009 |
| 20090004844 | Forming Complimentary Metal Features Using Conformal Insulator Layer A method is provided to form densely spaced metal lines. A first set of metal lines is formed by etching a first metal layer. A thin dielectric layer is conformally deposited on the first metal lines. A second metal is deposited on the thin dielectric layer, filling gap... | 01/01/2009 |
| 20080315418 | Methods of post-contact back end of line through-hole via integration Presented are methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. In one embodiment, the method comprises forming metal plug contacts through ... | 12/25/2008 |
| 20080299761 | Interconnection process An interconnection process is provided. The process includes the following steps. Firstly, a semiconductor base having at least a electrical conductive region is provided. Next, a dielectric layer with a contact hole is formed to cover the semiconductor base, wherein th... | 12/04/2008 |
| 20080299762 | Method for forming interconnects for 3-D applications A method for forming an interconnect, comprising (a) providing a substrate (203) with a via (205) defined therein; (b) forming a seed layer (211) such that a first portion of the seed layer extends over a surface of the via, and a second portion of ... | 12/04/2008 |
| 20080299718 | DAMASCENE PROCESS HAVING RETAINED CAPPING LAYER THROUGH METALLIZATION FOR PROTECTING LOW-K DIELECTRICS A method of forming single or dual damascene interconnect structures using either a via-first or trench first approach includes the steps of providing a substrate surface having an etch-stop layer thereon, a low-k dielectric layer on the etch-stop layer, and a dielectri... | 12/04/2008 |
| 20080179716 | MULTILEVEL INTERCONNECTS STRUCTURE WITH SHIELDING FUNCTION AND FABRICATING METHOD THEREOF A method of fabricating multilevel interconnects comprising providing a substrate having a pixel array area and a logical circuit area, forming a first dielectric layer on the substrate, performing a first metallizing process on the first dielectric layer to form a firs... | 07/31/2008 |
| 20080160754 | METHOD FOR FABRICATING A MICROELECTRONIC CONDUCTOR STRUCTURE A method for fabricating a microelectronic structure includes forming a via aperture through a dielectric layer located over a substrate having a conductor layer therein, to expose the conductor layer. The conductor layer typically comprises a copper containing material... | 07/03/2008 |
| 20080146021 | METHOD OF FABRICATING METAL INTERCONNECTS AND INTER-METAL DIELECTRIC LAYER THEREOF A method of fabricating metal interconnects and an inter-metal dielectric layer thereof. A first metal interconnect pattern and a second metal interconnect pattern disposed thereon are formed on a substrate by plating processes. Subsequently, an inter-metal dielectric l... | 06/19/2008 |
| 20080122093 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME A semiconductor device and a method for manufacturing the same are provided. The semiconductor device can include a lower metal wiring formed over a semiconductor substrate. A first metal barrier layer can be formed over the lower metal wiring and an interlayer insulati... | 05/29/2008 |
| 20080054413 | SELF-ALIGNED DUAL SEGMENT LINER AND METHOD OF MANUFACTURING THE SAME A method of forming a dual segment liner covering a first and a second set of semiconductor devices is provided. The method includes forming a first liner and a first protective layer on top thereof, the first liner covering the first set of semiconductor devices; formi... | 03/06/2008 |
| 20080045004 | Post passivation interconnection schemes on top of IC chips A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the... | 02/21/2008 |
| 20070298605 | Method for forming planarizing copper in a low-k dielectric Methods of fabricating an interconnect, which fundamentally comprises forming a second conductive film (e.g., aluminum) over first conductive film (e.g., copper) deposited in an opening formed in a dielectric layer (e.g., low-k dielectric). The second conductive film ha... | 12/27/2007 |
| 20070111517 | CHEMICAL MECHANICAL POLISHING PROCESS A copper/barrier CMP process includes (a) providing a substrate having a bulk metal layer and a barrier layer; (b) polishing the substrate with a first hard polishing pad on a first platen to substantially remove an upper portion of the bulk metal layer, wherein the fir... | 05/17/2007 |
| 20070111497 | PROCESS FOR FORMING A REDUNDANT STRUCTURE Device and method of fabricating device. The device includes a dual damascene line having a metal line and a via, and a redundant liner arranged to divide the metal line. The method includes forming a trench in a metal stripe of a dual damascene line, depositing a barri... | 05/17/2007 |
| 20070082476 | Method of manufacturing semiconductor device A method of manufacturing a semiconductor device is provided. The method includes: (A) forming an insulating film with a porous structure on a substrate; (B) forming a trench in the insulating film, the trench being used for forming an interconnection; (C) depositing a ... | 04/12/2007 |
| 20070082479 | Chemical mechanical polishing techniques for integrated circuit fabrication The present invention provides methods for fabricating horizontal interconnect lines for use in semiconductor wafer fabrication. A dielectric layer is deposited on a dielectric stack having a planarized top surface. The dielectric layer is not planarized at this stage o... | 04/12/2007 |
| 20070077751 | METHOD OF RESTORING LOW-K MATERIAL OR POROUS LOW-K LAYER A method of restoring a low-k material is described, applied to a substrate with a low-k material thereon, wherein the substrate has been subject to a previous process that raised the k-value of the low-k material. The method includes performing a plasma treatment to th... | 04/05/2007 |
| 20070066052 | Semiconductor device having three-dimensional construction and method for manufacturing the same A semiconductor device includes: a silicon substrate; and a silicon oxide film disposed on the silicon substrate. The silicon oxide film includes a part, which separates from a surface of the silicon substrate, so that the silicon oxide film provides a three-dimensional... | 03/22/2007 |
| 20070066051 | Method for forming gate pattern for electronic device A method for forming a gate pattern for an electronic device, comprising steps of: providing a substrate, whereon a first photo-resist layer is formed; performing a first photo-lithography process so as to form a first pattern with a first width on the substrate; formin... | 03/22/2007 |
| 20070049008 | Method for forming a capping layer on a semiconductor device A method for making a semiconductor device includes forming a patterned dielectric overlying active circuitry, the patterned dielectric having a plurality of cavities. A diffusion barrier is formed over the patterned dielectric. A conductive layer is formed over the dif... | 03/01/2007 |
| 20070020918 | Substrate processing method and substrate processing apparatus The present invention provides a substrate processing method that can perform improved flattening and processing upon the formation of interconnects. The a substrate processing method includes a step of eliminating a level difference in a surface of a interconnect mater... | 01/25/2007 |
| 20070010088 | Semiconductor device and method of fabricating the same A semiconductor and a method of fabricating the same are provided. The method includes: forming an insulation layer on a substrate; forming a trench by selectively etching the insulation layer; electroplating a copper layer in the trench and on the insulation layer unde... | 01/11/2007 |
| 20070004195 | Plate-type fluorescent lamp and display device having the same An exemplary embodiment of a plate-type fluorescent lamp and a display device having the same includes an upper glass substrate; a lower glass substrate adhering opposite to the upper glass substrate; electrodes formed on external surfaces of the upper glass substrate a... | 01/04/2007 |
| 20060286797 | Grain boundary blocking for stress migration and electromigration improvement in CU interconnects Example embodiments of a structure and method for forming a copper interconnect having a doped region near a top surface. The doped region has implanted alloying elements that block grain boundaries and reduce stress and electro migration. In a first example embodiment,... | 12/21/2006 |
| 20060228881 | Structure and method for minimizing substrate effect on nucleation during sputtering of thin film resistors A method of improving nucleation during depositing of a film (2) on a surface (18-3) of a wafer, including performing a planarizing operation on the surface (18-3), the planarizing operation resulting in generation of dangling chemical... | 10/12/2006 |
| 20060172527 | Method for forming a defined recess in a damascene structure using a CMP process and a damascene structure The present invention provides a technique that enables the formation of a recessed upper surface of an interconnect line to form an inlaid barrier cap layer on top of an inter-connect line to exhibit improved characteristics with respect to electromigration, electrical... | 08/03/2006 |
| 20060172528 | Methods of manufacturing semiconductor devices Methods of manufacturing semiconductors are disclosed. One example method includes forming a trench through a dual damascene process, depositing a barrier metal layer on the overall surface, and depositing copper in the trench to form a copper line. The example method m... | 08/03/2006 |
| 20060172526 | Method for preventing edge peeling defect A method for improving edge peeling defect is disclosed in this invention. According to this invention, a wafer can be kept from the edge peeling defect of the prior art by introducing a step for removing the weakly adhesive films and the metal structures at the wafer e... | 08/03/2006 |
