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| Application No. | Application Title | Issue Date |
| 20120038037 | SEMICONDUCTOR STRUCTURES AND METHODS OF MANUFACTURE Semiconductor structures with airgaps and/or metal linings and methods of manufacture are provided. The method of forming an airgap in a wiring level includes forming adjacent wires in a dielectric layer. The method further includes forming a masking layer coincident wi... | 02/16/2012 |
| 20120009778 | MICRO ELECTRO-MECHANICAL SENSOR (MEMS) FABRICATED WITH RIBBON WIRE BONDS A micro electro-mechanical sensor is provided. The micro electro-mechanical sensor includes a substrate, and a conducting plane disposed on the substrate. A conducting via is disposed on the substrate, such as adjacent to the conducting plane. A plurality of ribbon cond... | 01/12/2012 |
| 20110241220 | AIR GAPS IN A MULTILAYER INTEGRATED CIRCUIT AND METHOD OF MAKING SAME A multilayer integrated circuit (IC) including a cross pattern of air gaps in a wiring layer and methods of making the multilayer IC are provided. The patterning of the air gaps is independent of the wiring layout. Patterns of air gaps including: parallel alternating st... | 10/06/2011 |
| 20110108989 | PROCESS FOR REVERSING TONE OF PATTERNS ON INTEGERATED CIRCUIT AND STRUCTURAL PROCESS FOR NANOSCALE FABRICATION A process to produce an airgap on a substrate having a dielectric layer comprises defining lines by lithography where airgaps are required. The lines' dimensions are shrunk by a trimming process (isotropic etching). The tone of the patterns is reversed by applying a pla... | 05/12/2011 |
| 20110027985 | SEMICONDUCTOR DEVICE HAVING AERIAL WIRING AND MANUFACTURING METHOD THEREOF A semiconductor device includes a first aerial wiring including a first wiring layer which is formed in an air gap and contains Cu as a main component and a via layer which is electrically connected to the first wiring layer, is formed in an inter-level insulating film ... | 02/03/2011 |
| 20100151671 | NOVEL AIR GAP INTEGRATION SCHEME Methods are provided for forming a structure that includes an air gap. In one embodiment, a method is provided for forming a damascene structure comprises depositing a porous low dielectric constant layer by a method including reacting an organosilicon compound and a po... | 06/17/2010 |
| 20090309230 | AIR GAP FORMATION AND INTEGRATION USING A PATTERNING CAP Methods for patterning films and their resulting structures. In an embodiment, an amorphous carbon mask is formed over a substrate, such as a damascene layer. A spacer layer is deposited over the amorphous carbon mask and the spacer layer is etched to form a spacer and ... | 12/17/2009 |
| 20090280638 | Process for Producing Air Gaps in Microstructures, Especially of the Air Gap Interconnect Structure Type for Integrated Circuits The invention relates to a process for producing at least one air gap in a microstructure, which comprises:
| 11/12/2009 |
| 20090200636 | SUB-LITHOGRAPHIC DIMENSIONED AIR GAP FORMATION AND RELATED STRUCTURE Sub-lithographic dimensioned air gap formation and related structure are disclosed. In one embodiment, a method includes forming a dielectric layer including interconnects on a substrate; depositing a cap layer on the dielectric layer; depositing a photoresist over the ... | 08/13/2009 |
| 20090166881 | AIR-GAP ILD WITH UNLANDED VIAS A spacer is adjacent to a conductive line. Vias that do not completely land on the conductive line land on the spacer and do not punch through into a volume below the spacer.... | 07/02/2009 |
| 20090108417 | Method and System for Providing a Continuous Impedance Along a Signal Trace in an IC Package A multi-layered integrated circuit chip package comprises a void layer that includes at least one void. The multi-layered integrated circuit chip package also includes an insulation layer that electrically insulates the void layer from a trace layer. At least one trace ... | 04/30/2009 |
| 20090042383 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE A method of forming a dielectric layer having an air gap to isolate adjacent wirings or a gate stack of the semiconductor device is provided. A method of fabricating a semiconductor device includes providing a semiconductor substrate on which a plurality of wirings are ... | 02/12/2009 |
| 20090008788 | METHOD OF FORMING A SEMICONDUCTOR DEVICE A method of forming a semiconductor device. A first wiring level is formed on a top surface of a substrate. The first wiring level includes alternating layers of a first dielectric material and a second dielectric material. The layers of the first dielectric material in... | 01/08/2009 |
| 20080299758 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE A high-density N-type diffusion layer 116 formed in a separation area 115 makes it possible to reduce a collector current flowing through a parasitic NPN transistor 102. Thus, a normal CMOS process can be used to provide a driving circuit and a data... | 12/04/2008 |
| 20080296775 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE In one aspect of the present invention, a semiconductor device may include a semiconductor substrate having a semiconductor element on an upper surface, a first dielectric film provided on the semiconductor substrate, a second dielectric film provided on the first diele... | 12/04/2008 |
| 20080274609 | Method and structure for low-K interlayer dielectric layer An integrated circuit interconnect structure. The structure includes a substrate and a layer of transistor elements overlying the substrate. A first interlayer dielectric layer is formed overlying the layer of transistor elements. An etch stop layer is formed overlying ... | 11/06/2008 |
| 20080266787 | On-Chip Interconnect-Stack Cooling Using Sacrificial Interconnect Segments The present invention relates to an integrated-circuit device and to a method for fabricating an integrated-circuit device with an integrated fluidic-cooling channel. The method comprises forming recesses in a dielectric layer sequence at desired lateral positions of el... | 10/30/2008 |
| 20080258311 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME A semiconductor device includes a first wiring layer, a second wiring layer and a third wiring layer. The first wiring layer is formed on a semiconductor substrate. The second and the third wiring layer wiring layers are arranged in a direction intersecting with the fir... | 10/23/2008 |
| 20080227286 | METHOD FOR MANUFACTURING AN INTERCONNECTION STRUCTURE WITH CAVITIES FOR AN INTEGRATED CIRCUIT The invention relates to a method for manufacturing a structure of electrical interconnections of the damascene type for an integrated circuit, comprising at least one level of interconnections, consisting of electrical conductors arranged on a substrate and separated f... | 09/18/2008 |
| 20080182404 | NOVEL AIR GAP INTEGRATION SCHEME Methods are provided for forming a structure that includes an air gap. In one embodiment, a method is provided for forming a damascene structure comprises depositing a porous low dielectric constant layer by a method including reacting an organosilicon compound and a po... | 07/31/2008 |
| 20080174017 | HYBRID INTERCONNECT STRUCTURE FOR PERFORMANCE IMPROVEMENT AND RELIABILITY ENHANCEMENT The present invention provides an interconnect structure (of the single or dual damascene type) and a method of forming the same, in which a dense (i.e., non-porous) dielectric spacer is present on the sidewalls of a dielectric material. More specifically, the inventive... | 07/24/2008 |
| 20080171432 | Circuit Structure with Low Dielectric Constant Regions and Method of Forming Same A method for manufacturing a circuit includes the step of providing a first wiring level comprising first wiring level conductors separated by a first wiring level dielectric material. A first dielectric layer with a plurality of inter connect openings and a plurality o... | 07/17/2008 |
| 20080166870 | Fabrication of Interconnect Structures Interconnect structures are fabricated by methods that comprise depositing a thin conformal passivation dielectric and/or diffusion barrier cap and/or hard mask by an atomic layer deposition or supercritical fluid based process.... | 07/10/2008 |
| 20080142923 | SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURE In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a semiconductor structure having a silicon-on-insulator (SOI) substrate and a dielectric region is disclosed. The dielectric region is adjacent... | 06/19/2008 |
| 20080138977 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME A semiconductor device includes a plurality of wirings disposed in parallel to each other and an insulating layer covering the wirings so that a void is defined between the wirings. Each wiring includes a metal wiring layer having a first side and a second side opposed ... | 06/12/2008 |
| 20080122106 | Method to generate airgaps with a template first scheme and a self aligned blockout mask A structure and method to produce an airgap on a substrate having a dielectric layer with a pattern transferred onto the dielectric layer and a self aligned block out mask transferred on the dielectric layer around the pattern.... | 05/29/2008 |
| 20080122031 | Vertical electrical device A vertical electrical device includes a region in a substrate extending from a surface of the substrate, the region having an inner wall and an outer wall circumscribing the inner wall. An inner electrically conductive layer is disposed on the inner wall and an outer el... | 05/29/2008 |
| 20080099876 | Manufacturing method of semiconductor device and semiconductor device The present invention provides a method of manufacturing a semiconductor device, which comprises steps of forming a plurality of wirings on a first insulting film formed on a semiconductor substrate so as to adjoin one another, forming a second insulating film on the fi... | 05/01/2008 |
| 20080093746 | SEMICONDUCTOR WAFER HAVING EMBEDDED ELECTROPLATING CURRENT PATHS TO PROVIDE UNIFORM PLATING OVER WAFER SURFACE A semiconductor wafer having multi-layer metallization structures that are fabricated to include embedded interconnection structures which serve as low-resistance electroplating current paths to conduct bulk electroplating current fed to portions of a metallic seed laye... | 04/24/2008 |
| 20080070401 | Memory device and method for manufacturing the same A memory device and a method for fabricating the same provide a device capable of increasing or maximizing the performance of a microstructure device. The device includes: a plurality of word lines formed with a gap therebetween and extending in parallel with each other... | 03/20/2008 |
| 20080044999 | Method for an improved air gap interconnect structure In one embodiment, an apparatus comprises a first layer having at least one interconnect formed in an interlayer dielectric (ILD), a second layer formed over the first layer having a second at least one interconnect, a third layer formed over the second layer, the third... | 02/21/2008 |
| 20080038916 | METHOD FOR THE PRODUCTION OF PLANAR STRUCTURES A method for the production of a planar structure is disclosed. The method comprises producing on a substrate a plurality of structures of substantially equal height, and there being a space in between the plurality of structures. The method further comprises providing ... | 02/14/2008 |
| 20070224726 | THIN FILM PLATE PHASE CHANGE RAM CIRCUIT AND MANUFACTURING METHOD A memory device comprising a access circuits, an electrode layer over the access circuits, an array of phase change memory bridges over the electrode layer, and a plurality of bit lines over the array of phase change memory bridges. The electrode layer includes electrod... | 09/27/2007 |
| 20070155159 | Method for forming under a thin layer of a first material portions of another material and/ or empty areas A method for forming a empty area under a layer of a given material, including forming on a substrate a stacking of a photosensitive layer and of a layer of the given material; insolating a portion of the photosensitive layer or its complement according to whether the p... | 07/05/2007 |
| 20070148804 | Method of making a multilayered device with ultra-thin freestanding metallic membranes using a peel off process A micro electromechanical device includes a substrate having stacked films. Each of the films includes a first layer and a second layer. The second layer is metal of a predetermined thickness. The stacked films are formed by electroplating the second layer on the first ... | 06/28/2007 |
| 20070141829 | Semiconductive device fabricated using subliming materials to form interlevel dielectrics The invention provides a method of fabricating a semiconductive device [200]. In this embodiment, the method comprises depositing a hydrocarbon layer [294] over a semiconductive substrate, forming an interconnect structure [295, 297] within the hydr... | 06/21/2007 |
| 20070134908 | Fabrication of cooling and heat transfer systems by electroforming A process for the fabrication of a metallic component, such as those used in energy generation and heat transfer systems (e.g., reactor vessels, combustion chambers), in propulsion systems (e.g., rocket engines), and communications (e.g., optical telescopes). The proces... | 06/14/2007 |
| 20070123026 | Semiconductor device having high frequency components and manufacturing method thereof A transistor is located on a GaAs substrate. An air bridge extends to provide a cavity above gate electrodes of the transistor. An opening is sealed by the end ball of a second wire. Further, the semiconductor device is wholly covered by sealing resin. ... | 05/31/2007 |
| 20070090531 | Method of forming an electrical isolation associated with a wiring level on a semiconductor wafer A method of forming a wiring level and an electrical isolation associated with the wiring level on a surface of a semiconductor wafer comprises the steps of providing the semiconductor wafer having said surface, forming a plurality of electrically conductive wiring line... | 04/26/2007 |
| 20070069327 | Method for manufacturing an integrated semiconductor device In a method for manufacturing an integrated semiconductor device with low capacitive coupling between a conductive member and a via, a semiconductor substrate with a surface is provided. The conductive member is formed on the surface of the substrate wherein the conduct... | 03/29/2007 |
