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| Application No. | Application Title | Issue Date |
| 20120129334 | SEMICONDUCTOR PACKAGES AND METHODS OF MANUFACTURING THE SAME Provided are semiconductor packages and methods of manufacturing the semiconductor package. The semiconductor packages may include a substrate including a chip pad, a redistributed line which is electrically connected to the chip pad and includes an opening. The semicon... | 05/24/2012 |
| 20120129333 | METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE MANUFACTURED USING THE SAME Provided are a method for manufacturing a semiconductor package and a semiconductor package manufactured using the method. The method includes providing a substrate having a first region and a second region having a higher step difference than the first region, i.e., ha... | 05/24/2012 |
| 20120104604 | CRACK ARREST VIAS FOR IC DEVICES An integrated circuit (IC) device includes a substrate having a top surface including active circuitry including a plurality of I/O nodes, and a plurality of die pads coupled to the plurality of I/O nodes. A first dielectric layer including first dielectric vias is over... | 05/03/2012 |
| 20120108015 | UNDERFILL FLOW GUIDE STRUCTURES AND METHOD OF USING SAME Underfill flow guide structures and methods of using the same are provided with a module. In particular the underfill flow guide structures are integrated with a substrate and are configured to prevent air entrapment from occurring during capillary underfill processes.... | 05/03/2012 |
| 20120104602 | SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND CIRCUIT DEVICE USING SEMICONDUCTOR DEVICE [Problem] A semiconductor device which achieves a fine pitch, a high throughput and a high connection reliability, especially in flip-chip mounting is provided. A method for manufacturing the semiconductor device and a circuit device using the semiconductor device are a... | 05/03/2012 |
| 20120104601 | Semiconductor Device and Method of Forming Wafer Level Ground Plane and Power Ring A semiconductor die has active circuits formed on its active surface. Contact pads are formed on the active surface of the semiconductor die and coupled to the active circuits. A die extension region is formed around a periphery of the semiconductor die. Conductive THVs... | 05/03/2012 |
| 20120083113 | CREATION OF LEAD-FREE SOLDER JOINT WITH INTERMETALLICS A method of coupling an integrated circuit to a substrate includes providing the substrate, forming a contact pad in the substrate, contacting the contact pad with a solder ball, and repeatedly exposing the solder ball to a thermal process to cause intermetallics based ... | 04/05/2012 |
| 20120068334 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF Semiconductor devices of embodiments include a plurality of solder bumps electrically connected on a plurality of electrode pads disposed on a semiconductor substrate in parallel at a pitch of 40 μm or less via under bump metals. The ratio of the diameter (the top diam... | 03/22/2012 |
| 20120068337 | Semiconductor Device and Method of Forming Composite Bump-on-Lead Interconnection A semiconductor device has a semiconductor die mounted to a substrate with a plurality of composite interconnects formed between interconnect sites on the substrate and bump pads on the die. The interconnect sites are part of traces formed on the substrate. The intercon... | 03/22/2012 |
| 20120068339 | VLSI Package for High Performance Integrated Circuit A packaged integrated circuit is presented for placement on a printed circuit board (PCB) layer providing power lines and data access channels. The packaged integrated circuit includes; a package substrate having data channels and power lines; a circuit substrate having... | 03/22/2012 |
| 20120049343 | CONDUCTIVE CONNECTION STRUCTURE WITH STRESS REDUCTION ARRANGEMENT FOR A SEMICONDUCTOR DEVICE, AND RELATED FABRICATION METHOD A semiconductor device disclosed herein includes a conductive connection structure having a stepped profile that serves as a stress relief feature. The conductive connection structure includes a stress buffer arrangement for a contact pad. The stress buffer arrangement ... | 03/01/2012 |
| 20120049322 | Cylindrical Embedded Capacitors A device includes a substrate having a front surface and a back surface opposite the front surface. A capacitor is formed in the substrate and includes a first capacitor plate; a first insulation layer encircling the first capacitor plate; and a second capacitor plate e... | 03/01/2012 |
| 20120052677 | Method for Forming Lead-Free Solder Balls with a Stable Oxide Layer Based on a Plasma Process Solder balls of semiconductor devices and, in particular, lead-free solder balls receive a very uniform passivation layer, for instance in the form of an oxide layer, which is formed by applying a plasma treatment. For example, the passivation layer may be provided with... | 03/01/2012 |
| 20120049358 | Semiconductor Device and Semiconductor Process for Making the Same The present invention relates to a semiconductor device and a semiconductor process for making the same. The semiconductor device of the present invention includes a semiconductor substrate, at least one conductive via and at least one insulation ring. The semiconductor... | 03/01/2012 |
| 20120032335 | ELECTRONIC COMPONENT AND METHOD FOR MANUFACTURING THE SAME An electronic component including a wiring board having a power-source pattern and a signal pattern, a semiconductor element mounted on the wiring board and having a power-source electrode pad and a signal electrode pad, a first connection portion being made of a conduc... | 02/09/2012 |
| 20120032167 | SEMICONDUCTOR PACKAGE AND METHOD OF TESTING SAME A packaged integrated circuit includes a substrate having a wire layout pattern and a solder mask layer. An integrated circuit attached to a surface of the substrate is electrically connected to the wire layout pattern. An encapsulation material covers at least the inte... | 02/09/2012 |
| 20120025373 | Semiconductor Device and Method of Forming Vertically Offset Bond on Trace Interconnects on Different Height Traces A method of making a semiconductor device includes providing a substrate, and forming a first conductive layer over the substrate. A patterned layer is formed over the first conductive layer. A second conductive layer is formed in the patterned layer. A height of the se... | 02/02/2012 |
| 20120018851 | METAL-CONTAMINATION-FREE THROUGH-SUBSTRATE VIA STRUCTURE A through-substrate via (TSV) structure that is immune to metal contamination due to a backside planarization process is provided. After forming a through-substrate via (TSV) trench, a diffusion barrier liner is conformally deposited on the sidewalls of the TSV trench. ... | 01/26/2012 |
| 20120018876 | Multi-Die Stacking Using Bumps with Different Sizes A device includes a first die having a first side and a second side opposite to first side, the first side includes a first region and a second region, and a first metal bump of a first horizontal size formed on the first region of the first side of the first die. A sec... | 01/26/2012 |
| 20120018892 | SEMICONDUCTOR DEVICE WITH INDUCTOR AND FLIP-CHIP Semiconductor devices comprising a flip-chip having vias to connect front and back surfaces and a bondwire connected to the via or the back surface. Provision is made for packaging the flip-chip with a package substrate. | 01/26/2012 |
| 20120018886 | INTEGRATED CIRCUIT PACKAGE WITH OPEN SUBSTRATE AND METHOD OF MANUFACTURING THEREOF A method of manufacturing an integrated circuit package includes: forming a substrate including: forming a core layer, and forming vias in the core layer; forming a conductive layer having a predetermined thickness on the core layer and having substantially twice the pr... | 01/26/2012 |
| 20120009783 | Solder Bump With Inner Core Pillar in Semiconductor Package A flip chip semiconductor package has a substrate with a plurality of active devices. A contact pad is formed on the substrate in electrical contact with the plurality of active devices. A passivation layer, second barrier layer, and adhesion layer are formed between th... | 01/12/2012 |
| 20120007230 | CONDUCTIVE BUMP FOR SEMICONDUCTOR SUBSTRATE AND METHOD OF MANUFACTURE An embodiment of the disclosure includes a conductive bump on a semiconductor die. A substrate is provided. A bond pad is over the substrate. An under bump metallurgy (UBM) layer is over the bond pad. A copper pillar is over the UBM layer. The copper pillar has a top su... | 01/12/2012 |
| 20120009776 | SEMICONDUCTOR SUBSTRATES WITH UNITARY VIAS AND VIA TERMINALS, AND ASSOCIATED SYSTEMS AND METHODS Semiconductor substrates with unitary vias and via terminals, and associated systems and methods are disclosed. A representative method in accordance with a particular embodiment includes forming a blind via in a semiconductor substrate, applying a protective layer to a... | 01/12/2012 |
| 20120007231 | METHOD OF FORMING CU PILLAR CAPPED BY BARRIER LAYER A nickel barrier layer is formed on an upper sidewall surface of a Cu pillar. A mask layer with an opening for defining the Cu pillar window has an upper portion and a lower portion. The upper portion of the mask layer is removed after the formation of the Cu pillar so ... | 01/12/2012 |
| 20120007228 | CONDUCTIVE PILLAR FOR SEMICONDUCTOR SUBSTRATE AND METHOD OF MANUFACTURE An embodiment of the disclosure includes a conductive pillar on a semiconductor die. A substrate is provided. A bond pad is over the substrate. A conductive pillar is over the bond pad. The conductive pillar has a top surface, edge sidewalls and a height. A cap layer is... | 01/12/2012 |
| 20120009775 | SEMICONDUCTOR PACKAGE WITH A REDUCED VOLUME AND THICKNESS AND CAPABLE OF HIGH SPEED OPERATION AND METHOD FOR FABRICATING THE SAME A semiconductor package includes a semiconductor chip provided with a bonding pad disposed over a surface thereof; a through electrode passing from the surface to a second surface opposing the first surface and connected electrically with the bonding pad; and a redistri... | 01/12/2012 |
| 20120001329 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME A semiconductor package and a method for fabricating the same. The semiconductor package includes a first substrate including a first pad, a second substrate spaced apart from the first substrate and where a second pad is formed to face the first pad, a first bump elect... | 01/05/2012 |
| 20110316132 | Semiconductor Device and Method of Forming Vertically Offset Bond on Trace Interconnect Structure on Leadframe A semiconductor device has a vertically offset BOT interconnect structure. The vertical offset is achieved with a leadframe having a plurality of lead fingers around a die paddle. A first conductive layer is formed over the lead fingers. A second conductive layer is for... | 12/29/2011 |
| 20110318918 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE ALLOWING SMOOTH BUMP SURFACE A method of fabricating a semiconductor device, includes: removing, after forming solder for forming a plurality of bumps on a semiconductor substrate, an oxide film formed on a surface of the solder while heating the semiconductor substrate with first radiant heat; and... | 12/29/2011 |
| 20110318876 | SEMICONDUCTOR PACKAGE, ELECTRICAL AND ELECTRONIC APPARATUS INCLUDING THE SEMICONDUCTOR PACKAGE, AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE In one embodiment, a semiconductor package may include a semiconductor chip having a chip pad formed on a first surface thereof, a sealing member for sealing the semiconductor chip and exposing the first surface of the semiconductor chip, a conductive wiring overlying a... | 12/29/2011 |
| 20110317385 | WAFER LEVEL PACKAGE (WLP) DEVICE HAVING BUMP ASSEMBLIES INCLUDING A BARRIER METAL WLP semiconductor devices include bump assemblies that have a barrier layer for inhibiting electromigration within the bump assemblies. In an implementation, the bump assemblies include copper posts formed on the integrated circuit chips of the WLP devices. Barrier laye... | 12/29/2011 |
| 20110316154 | SEMICONDUCTOR DEVICE HAVING SEMICONDUCTOR SUBSTRATE, AND METHOD OF MANUFACTURING THE SAME A semiconductor device includes a semiconductor substrate having a plurality of electrode pads, a protective film covering the upper surface of the semiconductor substrate and having an opening so that the electrode pad is exposed therethrough, a metal film formed on th... | 12/29/2011 |
| 20110309490 | Plasma Treatment for Semiconductor Devices A semiconductor device having a polymer layer and a method of fabricating the same is provided. A two-step plasma treatment for a surface of the polymer layer includes a first plasma process to roughen the surface of the polymer layer and loosen contaminants, and a seco... | 12/22/2011 |
| 20110309492 | INTEGRATED CIRCUIT SYSTEM WITH RECESSED THROUGH SILICON VIA PADS AND METHOD OF MANUFACTURE THEREOF A method of manufacture of an integrated circuit system includes: providing a substrate with a face surface having a via therein and a back surface having a trench therein; filling the via with a conductive pillar; forming a recessed contact pad in the trench; filling t... | 12/22/2011 |
| 20110309502 | SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND MANUFACTURING APPARATUS FOR SEMICONDUCTOR DEVICE According to one embodiment, a semiconductor device includes a first semiconductor element, a first electrode, a ball part, a second electrode, and a wire. The first electrode is electrically connected to the first semiconductor element. The ball part is provided on the... | 12/22/2011 |
| 20110300705 | MANUFACTURING METHOD OF BUMP STRUCTURE WITH ANNULAR SUPPORT A manufacturing method of a bump structure with an annular support includes the following steps. A substrate including pads and a passivation layer is provided. The passivation has first openings exposing a portion of the pads. An UBM material layer is formed to cover t... | 12/08/2011 |
| 20110291266 | SEMICONDUCTOR INTEGRATED CIRCUIT HAVING A MULTI-CHIP STRUCTURE A semiconductor integrated circuit having a multi-chip structure includes a plurality of stacked semiconductor chips. At least one of the semiconductor chips includes first and second metal layers separately formed inside the semiconductor chip, a first internal circuit... | 12/01/2011 |
| 20110278716 | METHOD OF FABRICATING BUMP STRUCTURE A method for fabricating bump structure forms an under-bump metallurgy (UBM) layer in an opening of an encapsulating layer, and then forms a bump layer on the UBM layer within the opening of the encapsulating layer. After removing excess material of the bump layer from ... | 11/17/2011 |
| 20110272799 | IC CHIP AND IC CHIP MANUFACTURING METHOD THEREOF An IC chip and an IC chip manufacturing method thereof are provided. The IC chip has a chip body and at least one bump. The chip body has at least one conducting area on its surface. The bump is formed on the conducting area of the chip body. The bump includes a plurali... | 11/10/2011 |
