Did You Know...
...Chester Carlson was a patent agent who tired of having to make multiple copies of patent applications using the only duplication method available at the time: carbon paper. In 1959 he came up with a new copying system and took it to IBM for evaluation. The "experts" at IBM determined potential sales to be only 5,000 units because people wouldn't want to use a bulky machine when they had carbon paper. Carlson's invention was the xerography process, the company founded on the system is Xerox.
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| Application No. | Application Title | Issue Date |
| 20110237041 | ALTERNATING-DOPING PROFILE FOR SOURCE/DRAIN OF A FET A semiconductor device is provided. In an embodiment, the device includes a substrate and a transistor formed on the semiconductor substrate. The transistor may include a gate structure, a source region, and a drain region. The drain region includes an alternating-dopin... | 09/29/2011 |
| 20110001196 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME A semiconductor device includes a substrate of a first conductive type, a first doped region of a second conductive type, at least one second doped region of the first conductive type, a third doped region of the second conductive type, a gate structure, and at least on... | 01/06/2011 |
| 20100301414 | HIGH VOLTAGE NMOS WITH LOW ON RESISTANCE AND ASSOCIATED METHODS OF MAKING High voltage NMOS devices with low on resistance and associated methods of making are disclosed herein. In one embodiment, a method for making N typed MOSFET devices includes forming an N-well and a P-well with twin well process, forming field oxide, forming gate compri... | 12/02/2010 |
| 20100124809 | METHOD FOR FORMING A SHALLOW JUNCTION REGION USING DEFECT ENGINEERING AND LASER ANNEALING A method for forming a shallow junction region in a crystalline semiconductor substrate and method for fabricating a semiconductor device having the shallow junction region includes a defect engineering step in which first ions are introduced into a first region of the ... | 05/20/2010 |
| 20090321845 | SHORT CHANNEL LV, MV, AND HV CMOS DEVICES Low voltage, middle voltage and high voltage CMOS devices have upper buffer layers of the same conductivity type as the sources and drains that extend under the sources and drains and the gates but not past the middle of the gates, and lower bulk buffer layers of the op... | 12/31/2009 |
| 20090230468 | LDMOS DEVICES WITH IMPROVED ARCHITECTURES An LDMOS device includes a substrate of a first conductivity type, an epitaxial layer on the substrate, a buried well of a second conductivity type opposite to the first conductivity type in a lower portion of the epitaxial layer, the epitaxial layer being of the first ... | 09/17/2009 |
| 20090191684 | Novel Approach to Reduce the Contact Resistance A method for fabricating a semiconductor device is disclosed. First, a semiconductor substrate having a doped region(s) is provided. Thereafter, a pre-amorphous implantation process and neutral (or non-neutral) species implantation process is performed over the doped re... | 07/30/2009 |
| 20090179275 | SEMICONDUCTOR MEMORY DEVICE JUNCTION AND METHOD OF FORMING THE SAME The present invention relates to semiconductor memory device junction and a method of forming the same. The semiconductor memory device junction may include a semiconductor substrate having gate lines formed thereon, and a junction having first and second junction eleme... | 07/16/2009 |
| 20090096039 | HIGH-VOLTAGE DEVICE AND MANUFACTURING METHOD OF TOP LAYER IN HIGH-VOLTAGE DEVICE A high-voltage device including a first conductive type substrate, a gate, a second conductive type well, a second conductive type source region, a second conductive type drain region, conductive layers, and a first conductive type top layer. The gate is disposed on the... | 04/16/2009 |
| 20090068812 | Method of Forming Memory Devices by Performing Halogen Ion Implantation and Diffusion Processes Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures... | 03/12/2009 |
| 20090026553 | Tunnel Field-Effect Transistor with Narrow Band-Gap Channel and Strong Gate Coupling A semiconductor device and the methods of forming the same are provided. The semiconductor device includes a low energy band-gap layer comprising a semiconductor material; a gate dielectric on the low energy band-gap layer; a gate electrode over the gate dielectric; a f... | 01/29/2009 |
| 20080290412 | SUPPRESSING SHORT CHANNEL EFFECTS An apparatus comprising a substrate of first dopant type and first dopant concentration; pocket regions in the substrate and having the first dopant type and a second dopant concentration greater than the first dopant concentration; a gate stack over the substrate and l... | 11/27/2008 |
| 20080283911 | High-voltage semiconductor device and method for manufacturing the same A high-voltage semiconductor device and a method for manufacturing the same are disclosed. The disclosed high-voltage semiconductor device includes a semiconductor substrate, a first N type well in the semiconductor substrate, a first P type well in the first N type wel... | 11/20/2008 |
| 20080160711 | Contactless flash memory array A method for forming a contactless flash memory cell array is disclosed. According to an embodiment of the invention, a plurality of active regions is formed on a substrate. An insulating layer is then deposited over the active regions, and a portion of the insulating l... | 07/03/2008 |
| 20080132024 | Method of manufacturing double diffused drains in semiconductor devices A method of manufacturing double diffused drains in a semiconductor device. An embodiment comprises forming a gate dielectric layer on a substrate, and masking and patterning the gate dielectric layer. Once the gate dielectric layer has been patterned, a second dielectr... | 06/05/2008 |
| 20080099852 | Integrated semiconductor device and method of manufacturing an integrated semiconductor device An integrated semiconductor device includes at least one transistor. A first and a second source/drain diffusion region are arranged in a doped well. A contact structure is arranged on or above the substrate surface and abuts the lateral sidewall of a gate electrode iso... | 05/01/2008 |
| 20070138551 | High voltage semiconductor device and method for fabricating the same There is provided a high voltage semiconductor device comprising: a semiconductor substrate of a first conductivity type, including a first region, a second region relatively lower than the first region, and a sloped region between the first region and the second region... | 06/21/2007 |
| 20070132018 | Semiconductor device and method for producing the same A semiconductor device, including a first MIS-type transistor formed in a first region of a semiconductor region, the first region being of a first conductivity type, the first MIS-type transistor including: a first gate insulating film formed on the first region; a fir... | 06/14/2007 |
| 20070114604 | Double-extension formation using offset spacer A MOS transistor structure is disclosed. A gate electrode is disposed on a semiconductor substrate. A first extension of a predetermined impurity type is substantially aligned with the gate electrode in the substrate. A second extension of the predetermined impurity typ... | 05/24/2007 |
| 20070102759 | Method for forming an integrated circuit with high voltage and low voltage devices A method is disclosed for integrally forming at least one low voltage device and at least one high voltage device. According to the method, a first gate structure and a second gate structure are formed on a semiconductor substrate, wherein the first and second gate stru... | 05/10/2007 |
| 20070034949 | Semiconductor device having multiple source/drain extension implant portions and a method of manufacture therefor The present invention provides a semiconductor device, a method for manufacturing therefore, and an integrated circuit including the same. The semiconductor device, in one advantageous embodiment, includes a gate structure (230) located over a substrate (210 | 02/15/2007 |
| 20060194398 | Semiconductor device and its manufacturing method A semiconductor device which has a source/drain extension structure suitable for miniaturization, is provided a semiconductor device comprising a gate electrode formed on a semiconductor substrate of a first conductivity type via a gate insulator, a semiconductor region... | 08/31/2006 |
| 20060177983 | Method for forming a notched gate Methods for forming notched gates and semiconductor devices utilizing the notched gates are provided. The methods utilize the formation of a dummy gate on a substrate. The dummy gate is etched to form notches in the dummy gate, and sidewall spacers are formed on the sid... | 08/10/2006 |
| 20060148185 | Method for manufacturing high voltage transistor A method for manufacturing a high voltage transistor is disclosed. The method includes sequentially forming gate oxide films, polysilicon layers, and silicon nitride films on a semiconductor substrate; patterning the silicon nitride films, the polysilicon layers, and th... | 07/06/2006 |
| 20060071269 | High voltage MOS transistor with up-retro well A high voltage MOS transistor is provided that is compatible with low-voltage, sub-micron CMOS and BiCMOS processes. The high voltage transistor of the present invention has dopants that are implanted into the substrate prior to formation of the epitaxial layer. The imp... | 04/06/2006 |
| 20060051927 | Manufacture of insulated gate type field effect transistor After a field insulating film having an element opening is formed on the surface of a p-type well, a gate insulating film is formed on a semiconductor surface in the element opening. A gate electrode layer of polysilicon or the like is formed on the insulating film. By ... | 03/09/2006 |
| 20060043480 | Semiconductor device and fabrication method of the same A semiconductor device comprises a semiconductor layer which includes a terminate end part and a cell formation part that is surrounded by this end part, and a plurality of guard rings each of which is formed at the end part to surround the cell formation part. These gu... | 03/02/2006 |
| 20060033155 | Method of making and structure for LDMOS transistor A transistor of an integrated circuit is provided. A first doped well region is formed in a well layer at a first active region. At least part of the first doped well region is adjacent to a gate electrode of the transistor. A recess is formed in the first doped well re... | 02/16/2006 |
| 20050287753 | MOS device for high voltage operation and method of manufacture A high voltage semiconductor device. The high voltage device has a substrate (e.g., silicon wafer) having a surface region. The substrate has a well region within the substrate and a double diffused drain region within the well region. A gate dielectric layer is overlyi... | 12/29/2005 |
| 20050282346 | MIM capacitors A method for forming a MIM capacitor and a MIM capacitor device formed by same. A preferred embodiment comprises selectively forming a first cap layer over a wafer including a MIM capacitor bottom plate, and depositing an insulating layer over the MIM capacitor bottom p... | 12/22/2005 |
| 20050245037 | Method for fabricating flash memory device A method for fabricating a flash memory device is disclosed that improves hot carrier injection efficiency by forming a gate after forming source and drain implants using a sacrificial insulating layer pattern, which includes forming a sacrificial insulating pattern lay... | 11/03/2005 |
| 20050239258 | Method of fabricating semiconductor device An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the ... | 10/27/2005 |
| 20050227448 | High voltage double diffused drain MOS transistor with medium operation voltage A method of fabricating a high voltage MOS transistor with a medium operation voltage on a semiconductor wafer. The transistor has a double diffused drain (DDD) and a medium operation voltage such as 6 to 10 volts, which is advantageous for applications having both low ... | 10/13/2005 |
| 20050224872 | Semiconductor device and method for fabricating the same A semiconductor device of the present invention includes, as a peripheral MIS transistor 25b, a gate insulating film 13b and a gate electrode 14b provided above an active region 10b, first and second sidewalls 1... | 10/13/2005 |
| 20050205926 | High-voltage MOS transistor and method for fabricating the same A method for fabricating a high-voltage MOS transistor. A first doping region with a first dosage is formed in a substrate. A gate structure is formed overlying the substrate and partially covers the first doping region. The substrate is ion implanted using the gate str... | 09/22/2005 |
| 20050184338 | High voltage LDMOS transistor having an isolated structure A high voltage LDMOS transistor according to the present invention includes a P-field and divided P-fields in an extended drain region of a N-well. The P-field and divided P-fields form junction-fields in the N-well, in which a drift region is fully depleted before brea... | 08/25/2005 |
| 20050181567 | Double blanket ion implant method and structure A double blanket ion implant method for forming diffulsion regions in memory array devices, such as a MOSFET access device is disclosed. The method provides a semiconductor substrate with a gate structure formed on its surface Next, a first pair of diffulsion regions ar... | 08/18/2005 |
| 20050176207 | Method of manufacturing a semiconductor device In a method of manufacturing a semiconductor device, a device including gate electrodes and asymmetric source and drain regions is formed by employing a semiconductor layer structure. The short channel effect is prevented in the resulting device even though the gate ele... | 08/11/2005 |
| 20050164462 | Semiconductor device and fabricating method thereof A semiconductor device and fabricating method are provided, by which device drivability can be increased by forming second LDD regions after isolating first LDD regions from source/drain regions to prevent heavily doped impurities therein from diffusing into the first L... | 07/28/2005 |
| 20050156236 | MOS transistor with a three-step source/drain implant A new MOS transistor is described. The transistor has a source/drain region that comprises 3 portions. Each portion is the result of an separate ion implant step. The combination of the three portions of the source/drain region yields a transistor of superior performanc... | 07/21/2005 |
