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| Application No. | Application Title | Issue Date |
| 20120129310 | METHODS OF FABRICATING A SEMICONDUCTOR DEVICE HAVING A HIGH-K GATE DIELECTRIC LAYER AND SEMICONDUCTOR DEVICES FABRICATED THEREBY A method of fabricating a semiconductor device includes forming a lower interfacial layer on a semiconductor layer, the lower interfacial layer being a nitride layer, forming an intermediate interfacial layer on the lower interfacial layer, the intermediate interfacial ... | 05/24/2012 |
| 20120127795 | NON-VOLATILE MEMORY AND MANUFACTURING METHOD THEREOF AND OPERATING METHOD OF MEMORY CELL A non-volatile memory and a manufacturing method thereof and a method for operating a memory cell are provided. The non-volatile memory includes a substrate, first and second doped regions, a charged-trapping structure, first and second gates and an inter-gate insulatio... | 05/24/2012 |
| 20120104512 | SEALED AIR GAP FOR SEMICONDUCTOR CHIP A semiconductor chip including a substrate; a dielectric layer over the substrate; a gate within the dielectric layer, the gate including a sidewall; a contact contacting a portion of the gate and a portion of the sidewall; and a sealed air gap between the sidewall, the... | 05/03/2012 |
| 20120104509 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE A semiconductor device includes: a first conductivity type transistor and a second conductivity type transistor, wherein each of the first conductivity type transistor and the second conductivity type includes a gate insulating film formed on a base, a metal gate electr... | 05/03/2012 |
| 20120083086 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR There is provided a semiconductor device including a semiconductor substrate (10), a high concentration diffusion region (22) formed within the semiconductor substrate (10), a first low concentration region (24) that has a lower impurity conc... | 04/05/2012 |
| 20120070951 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREFOR There is provided a semiconductor device including bit lines (14) formed in a semiconductor substrate (10), insulating film lines (18) located on the bit lines (14) to successively run in a length direction of the bit lines (14), gate ... | 03/22/2012 |
| 20120068275 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME A method for fabricating a semiconductor device includes forming a high-dielectric constant insulating film including a high-dielectric constant film; forming a first conductive film including an oxide film on an upper surface thereof and containing at least one of high... | 03/22/2012 |
| 20120052645 | SEMICONDUCTOR DEVICE PRODUCTION METHOD A semiconductor device production method includes: forming a gate insulating film on the p-type region of a semiconductor substrate; forming a first aluminum oxide film with an oxygen content lower than stoichiometric composition on the gate insulating film; forming a t... | 03/01/2012 |
| 20120045879 | TUNNEL EFFECT TRANSISTORS BASED ON ELONGATE MONOCRYSTALLINE NANOSTRUCTURES HAVING A HETEROSTRUCTURE Tunnel field-effect transistors (TFETs) are regarded as successors of metal-oxide semiconductor field-effect transistors (MOSFETs), but silicon-based TFETs typically suffer from low on-currents, a drawback related to the large resistance of the tunnel barrier. To achiev... | 02/23/2012 |
| 20120045880 | METAL GATE TRANSISTOR AND METHOD FOR FABRICATING THE SAME A method for fabricating metal gate transistor is disclosed. The method includes the steps of: providing a substrate, wherein the substrate comprises a transistor region defined thereon; forming a gate insulating layer on the substrate; forming a stacked film on the gat... | 02/23/2012 |
| 20120038009 | Novel methods to reduce gate contact resistance for AC reff reduction A method (and semiconductor device) of fabricating a semiconductor device provides a field effect transistor (FET) with reduced gate contact resistance (and series resistance) for improved device performance. An impurity is implanted or deposited in the gate stack in an... | 02/16/2012 |
| 20120032280 | MOS TRANSISTORS INCLUDING SiON GATE DIELECTRIC WITH ENHANCED NITROGEN CONCENTRATION AT ITS SIDEWALLS A method of forming an integrated circuit (IC) having at least one MOS device includes forming a SiON gate dielectric layer on a silicon surface. A gate electrode layer is deposited on the SiON gate layer and then patterning forms a gate stack. Exposed gate dielectric s... | 02/09/2012 |
| 20120025287 | Memory Cell, An Array, And A Method for Manufacturing A Memory Cell A memory cell (100) comprising a transistor, the transistor comprising a substrate (101), a first source/drain region (102), a second source/drain region (112), a gate (104) and a gate insulating layer (103) positioned between t... | 02/02/2012 |
| 20120025327 | SEMICONDUCTOR DEVICE WITH METAL GATES AND METHOD FOR FABRICATING THE SAME A semiconductor device includes a gate insulation layer formed over a substrate and having a high dielectric constant, a gate electrode formed over the gate insulation layer and a work function control layer formed between the substrate and the gate insulation layer and... | 02/02/2012 |
| 20120028429 | METHOD OF FORMING A NON-VOLATILE ELECTRON STORAGE MEMORY AND THE RESULTING DEVICE The invention provides a method of forming an electron memory storage device and the resulting device. The device comprises a gate structure which, in form, comprises a first gate insulating layer formed over a semiconductor substrate, a self-forming electron trapping l... | 02/02/2012 |
| 20120024963 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME An object of this invention is to provide a semiconductor device (an RFID) with reduced loss of voltage/current corresponding to a threshold value of a transistor, and having a voltage/current rectification property. Another object of this invention is to simplify a fab... | 02/02/2012 |
| 20120018790 | NON-VOLATILE MEMORY AND FABRICATING METHOD THEREOF A non-volatile memory including a substrate, a stacked gate structure, two doped regions and a plurality of spacers is provided. The stacked gate structure is disposed on the substrate, wherein the stacked gate structure includes a first dielectric layer, a charge stora... | 01/26/2012 |
| 20120018795 | NON-VOLATILE MEMORY AND MANUFACTURING METHOD THEREOF A manufacturing method of a non-volatile memory is disclosed. A gate structure is formed on a substrate and includes a gate dielectric layer and a gate conductive layer. The gate dielectric layer is partly removed, thereby a symmetrical opening is formed among the gate ... | 01/26/2012 |
| 20120019284 | Normally-Off Field Effect Transistor, a Manufacturing Method Therefor and a Method for Programming a Power Field Effect Transistor A normally-off power field-effect transistor semiconductor structure is provided. The structure includes a channel, a source electrode, a gate electrode and trapped charges which arranged between the gate electrode and the channel such that the channel is in an off-stat... | 01/26/2012 |
| 20120015488 | HIGH-K GATE DIELECTRIC OXIDE A dielectric such as a gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO2 gate oxides are provided. Gate oxides formed from elements such as zirconium are thermodynamically stable... | 01/19/2012 |
| 20120012921 | MEMORY ARRAYS HAVING SUBSTANTIALLY VERTICAL, ADJACENT SEMICONDUCTOR STRUCTURES AND THE FORMATION THEREOF Memory arrays and methods of their formation are disclosed. One such memory array has memory-cell strings are formed adjacent to separated substantially vertical, adjacent semiconductor structures, where the separated semiconductor structures couple the memory cells of ... | 01/19/2012 |
| 20110315961 | Ultrathin Spacer Formation for Carbon-Based FET A method for formation of a carbon-based field effect transistor (FET) includes depositing a first dielectric layer on a carbon layer located on a substrate; forming a gate electrode on the first dielectric layer; etching an exposed portion of the first dielectric layer... | 12/29/2011 |
| 20110309434 | NONVOLATILE MEMORY DEVICE AND MANUFACTURING METHOD THEREOF A nonvolatile memory device and a manufacturing method thereof are provided. The manufacturing method includes the following steps. First, a substrate is provided. Then, a tunneling dielectric layer is formed on the substrate, and a dummy gate is form on the tunneling d... | 12/22/2011 |
| 20110303972 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME A semiconductor device manufacturing method of an embodiment includes the steps of: forming a first insulating layer on a semiconductor substrate; forming on the first insulating layer an amorphous or polycrystalline semiconductor layer having a narrow portion; forming ... | 12/15/2011 |
| 20110303968 | Nonvolatile Memory Array With Continuous Charge Storage Dielectric Stack An integrated circuit of an array of nonvolatile memory cells has a dielectric stack layer over the substrate, and implanted regions in the substrate under the dielectric stack layer. The dielectric stack layer is continuous over a planar region, that includes locations... | 12/15/2011 |
| 20110298061 | STRUCTURE AND METHOD FOR REPLACEMENT GATE MOSFET WITH SELF-ALIGNED CONTACT USING SACRIFICIAL MANDREL DIELECTRIC The present disclosure provides a method for forming a semiconductor device that includes forming a replacement gate structure overlying a channel region of a substrate. A mandrel dielectric layer is formed overlying source and drain regions of the substrate. The replac... | 12/08/2011 |
| 20110300682 | CHARGE TRAPPING DEVICES WITH FIELD DISTRIBUTION LAYER OVER TUNNELING BARRIER A memory cell comprising: a semiconductor substrate with a surface with a source region and a drain region disposed below the surface of the substrate and separated by a channel region; a tunneling barrier dielectric structure with an effective oxide thickness of greate... | 12/08/2011 |
| 20110291198 | Scaled Equivalent Oxide Thickness for Field Effect Transistor Devices A method for forming a field effect transistor device includes forming an oxide layer on a substrate, forming a dielectric layer on the oxide layer, forming a first TiN layer on the dielectric layer, forming a metallic layer on the first layer, forming a second TiN laye... | 12/01/2011 |
| 20110281412 | PRODUCTION OF A TRANSISTOR GATE ON A MULTIBRANCH CHANNEL STRUCTURE AND MEANS FOR ISOLATING THIS GATE FROM THE SOURCE AND DRAIN REGIONS A method for fabricating a microelectronic device comprising: a support, an etched stack of thin layers comprising: at least one first block and at least one second block resting on the support, in which at least one drain region and at least one source region, respecti... | 11/17/2011 |
| 20110272754 | MEMORIES AND THEIR FORMATION Memories and their formation are disclosed. One such memory has a first array of first memory cells extending in a first direction from a first surface of a semiconductor. A second array of second memory cells extends in a second direction, opposite to the first directi... | 11/10/2011 |
| 20110266604 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME A nonvolatile memory device includes a plurality of strings each having vertically-stacked active layers over a plurality of word lines, at least one bit line connection unit vertically formed over one end of the word lines and having a stairway shape, and a plurality o... | 11/03/2011 |
| 20110263091 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE Disclosed is a semiconductor device using an oxide semiconductor, with stable electric characteristics and high reliability. In a process for manufacturing a bottom-gate transistor including an oxide semiconductor film, dehydration or dehydrogenation is performed by hea... | 10/27/2011 |
| 20110254106 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD A semiconductor device includes a gate insulation film formed over a semiconductor substrate; a cap film formed over the gate insulation film; a silicon oxide film formed over the cap film; a metal gate electrode formed over the silicon oxide film; and source/drain diff... | 10/20/2011 |
| 20110256682 | Multiple Deposition, Multiple Treatment Dielectric Layer For A Semiconductor Device A method is provided for fabricating a semiconductor device. A semiconductor substrate is provided. A first high-k dielectric layer is formed on the semiconductor substrate. A first treatment is performed on the high-k dielectric layer. In an embodiment, the treatment i... | 10/20/2011 |
| 20110242888 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF The semiconductor device includes the nonvolatile memory cell in the main surface of a semiconductor substrate. The nonvolatile memory cell has a first insulating film over the semiconductor substrate, a conductive film, a second insulating film, the charge storage film... | 10/06/2011 |
| 20110241131 | SEMICONDUCTOR MEMORY DEVICE WITH BIT LINE OF SMALL RESISTANCE AND MANUFACTURING METHOD THEREOF A reduction of a resistance of a bit line of a memory cell array and a reduction of a forming area of the memory cell array are planed. Respective bit lines running at right angles to a word line are composed of a diffusion bit line formed in a semiconductor substrate a... | 10/06/2011 |
| 20110233649 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE A non-volatile semiconductor memory device includes: a charge accumulation layer (CAL) on a substrate; a memory gate formed onto the substrate through the CAL; a first side gate formed through a first insulating film on a first side of the memory gate; a second side gat... | 09/29/2011 |
| 20110233647 | METHODS FOR FORMING A MEMORY CELL HAVING A TOP OXIDE SPACER Methods for fabricating a semiconductor memory cell that has a spacer layer are disclosed. A method includes forming a plurality of source/drain regions in a substrate where the plurality of source/drain regions are formed between trenches, forming a first oxide layer a... | 09/29/2011 |
| 20110233689 | SEMICONDUCTOR DEVICE, PROCESS FOR PRODUCING SEMICONDUCTOR DEVICE, SEMICONDUCTOR SUBSTRATE, AND PROCESS FOR PRODUCING SEMICONDUCTOR SUBSTRATE There is provided a semiconductor device that includes a III-V Group compound semiconductor having a zinc-blende-type crystal structure, an insulating material being in contact with the (111) plane of the III-V Group compound semiconductor, a plane of the III-V Group co... | 09/29/2011 |
| 20110230028 | MANUFACTURING METHOD OF STRAIGHT WORD LINE NOR TYPE FLASH MEMORY ARRAY In a manufacturing method of a straight word line NOR flash memory array, a source line is implanted after the formation of a word line in the NOR type flash memory array is completed, and a discrete implant region is formed in the NOR type flash memory array and parall... | 09/22/2011 |
