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| Application No. | Application Title | Issue Date |
| 20120001249 | ULTRAHIGH DENSITY VERTICAL NAND MEMORY DEVICE & METHOD OF MAKING THEREOF Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extendi... | 01/05/2012 |
| 20110309424 | STRUCTURE OF MEMORY DEVICE AND PROCESS FOR FABRICTING THE SAME A structure of a memory cell of a static random memory device and a process for fabricating the same are disclosed. The memory cell includes a substrate having an active region including an N-well and a shallow trench isolation structure; a first gate and a second gate ... | 12/22/2011 |
| 20110263087 | Semiconductor Device and Manufacturing Method Thereof A semiconductor device which is formed in a self-aligned manner without causing a problem of misalignment in forming a control gate electrode and in which a leak between the control gate electrode and a floating gate electrode is not generated, and a manufacturing metho... | 10/27/2011 |
| 20110215393 | ON-CHIP PLASMA CHARGING SENSOR A device for monitoring charging effects includes a semiconductor substrate having a surface region. The device also includes first, second, and third doped regions spaced apart in the semiconductor substrate and a dielectric layer overlying the surface region. The devi... | 09/08/2011 |
| 20110189829 | METHODS OF FABRICATING NONVOLATILE MEMORY DEVICES HAVING STACKED STRUCTURES A memory device includes a first active region on a substrate and first and second source/drain regions on the substrate abutting respective first and second sidewalls of the first active region. A first gate structure is disposed on the first active region between the ... | 08/04/2011 |
| 20110140189 | ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY AND MANUFACTURING METHOD THEREOF An electrically erasable programmable read-only memory includes a first polysilicon layer, a second polysilicon layer and a third polysilicon layer, the first polysilicon layer and the third polysilicon layer forming a control gate and the second polysilicon layer formi... | 06/16/2011 |
| 20110070707 | METHOD OF MANUFACTURING NOR FLASH MEMORY In a method of manufacturing a NOR flash memory, two times of tilt ion implantation process are conducted to form a tilt-implanted source region, so as to improve the distribution of the source region in a semiconductor substrate and reduce the probability of short chan... | 03/24/2011 |
| 20110049603 | Reverse Disturb Immune Asymmetrical Sidewall Floating Gate Devices and Methods Circuits and methods for providing a floating gate structure comprising floating gate cells having improved reverse tunnel disturb immunity. A floating gate structure is formed over a semiconductor substrate comprising a floating gate, a charge trapping dielectric layer... | 03/03/2011 |
| 20110032762 | MULTI-DOT FLASH MEMORY According to one embodiment, a multi-dot flash memory includes an active area, a floating gate arranged on the active area via a gate insulating film and having a first side and a second side facing each other in a first direction, a word line arranged on the floating g... | 02/10/2011 |
| 20100301403 | SEMICONDUCTOR DEVICE WITH MULTIPLE GATES AND DOPED REGIONS AND METHOD OF FORMING A semiconductor device includes a source region within a semiconductor substrate, a drain region within the semiconductor substrate, a control gate over the semiconductor substrate and between the source region and the drain region, a first gate between the control gate... | 12/02/2010 |
| 20100296340 | NANOTUBE MEMORY CELL WITH FLOATING GATE BASED ON PASSIVATED NANOPARTICLES AND MANUFACTURING PROCESS THEREOF A method for manufacturing a nanotube non-volatile memory cell is proposed. The method includes the steps of: forming a source electrode and a drain electrode, forming a nanotube implementing a conduction channel between the source electrode and the drain electrode, for... | 11/25/2010 |
| 20100244116 | METHOD OF FORMING AN EEPROM DEVICE AND STRUCTURE THEREFOR In one embodiment, an EEPROM device is formed to include a metal layer having an opening therethrough. The opening overlies a portion of a floating gate of the EEPROM device.... | 09/30/2010 |
| 20100219459 | METHOD FOR MANUFACTURING A NON-VOLATILE MEMORY, NON-VOLATILE MEMORY DEVICE, AND AN INTEGRATED CIRCUIT A method of manufacturing a non-volatile memory device, including providing at least one control gate layer on a substrate. A passage may be created between the at least one control gate layer and the substrate. In the passage at least one filling layer may be provided.... | 09/02/2010 |
| 20100200908 | Nonvolatile memory device and method of fabricating the same Provided are a nonvolatile memory device having a vertical folding structure and a method of manufacturing the nonvolatile memory device. A semiconductor structure includes first and second portions that are substantially vertical. A plurality of memory cells are arrang... | 08/12/2010 |
| 20100187594 | SEMICONDUCTOR MEMORY AND METHOD OF MANUFACTURING THE SAME A semiconductor memory includes a semiconductor substrate, a buried insulating film formed on a part of an upper surface of the semiconductor substrate, and a semiconductor layer formed on another part of the upper surface of the semiconductor substrate. Each of the mem... | 07/29/2010 |
| 20100167479 | EMBEDDED TRAP DIRECT TUNNEL NON-VOLATILE MEMORY The cell comprises a substrate having a drain region and a source region. An oxynitride layer is formed over the substrate. An embedded trap layer is formed over the oxynitride layer. An injector layer is formed over the embedded trap layer. A high dielectric constant l... | 07/01/2010 |
| 20100159655 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY DEVICES A semiconductor memory device has a floating gate formed on a semiconductor substrate at certain intervals along a plane with a first insulator interposed therebetween, and a control gate formed on the layer of floating gates with a second insulator interposed therebetw... | 06/24/2010 |
| 20100148238 | NON-VOLATILE MEMORY AND FABRICATING METHOD THEREOF A non-volatile memory is formed on a substrate. The non-volatile memory includes an isolation structure, a floating gate, and a gate dielectric layer. The isolation structure is disposed in the substrate to define an active area. The floating gate is disposed on the sub... | 06/17/2010 |
| 20100085811 | SCALED DOWN SELECT GATES OF NAND FLASH MEMORY CELL STRINGS AND METHOD OF FORMING SAME A NAND flash memory cell string having scaled down select gates. The NAND flash memory cell string includes a first select gate that has a width of 140 nm or less and a plurality of wordlines that are coupled to the first select gate. Gates associated with the plurality... | 04/08/2010 |
| 20100072538 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME A nonvolatile semiconductor memory device includes a plurality of memory strings, each of which has a plurality of electrically rewritable memory cells connected in series; and select transistors, one of which is connected to each of ends of each of the memory strings. ... | 03/25/2010 |
| 20100075467 | NON-VOLATILE ELECTROMECHANICAL FIELD EFFECT DEVICES AND CIRCUITS USING SAME AND METHODS OF FORMING SAME Non-volatile field effect devices and circuits using same. A non-volatile field effect device includes a source, drain and gate with a field-modulatable channel between the source and drain. Each of the source, drain, and gate have a corresponding terminal. An electrome... | 03/25/2010 |
| 20100052034 | FLASH MEMORY GATE STRUCTURE FOR WIDENED LITHOGRAPHY WINDOW A first portion of a semiconductor substrate belonging to a flash memory device region is recessed to a recess depth to form a recessed region, while a second portion of the semiconductor substrate belonging to a logic device region is protected with a masking layer. A ... | 03/04/2010 |
| 20100041194 | SEMICONDUCTOR DEVICE WITH SPLIT GATE MEMORY CELL AND FABRICATION METHOD THEREOF A split gate memory cell. First and second well regions of respectively first and second conductivity types are formed in the substrate. A floating gate is disposed on a junction of the first and second well regions and insulated from the substrate. A control gate is di... | 02/18/2010 |
| 20100003795 | Method for Fabricating Flash Memory Device Having Vertical Floating Gate A method for fabricating a flash memory device includes forming a control gate having a hollow donut shape over an insulation layer formed over a substrate. The method also includes forming an inter-poly dielectric of a spacer shape on an inner wall of the control gate,... | 01/07/2010 |
| 20090303797 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME A semiconductor device includes a semiconductor substrate, a gate insulating film formed on the substrate, a first gate electrode formed on the gate insulating film, source and drain regions formed in the substrate so as to sandwich the first gate electrode, an intergat... | 12/10/2009 |
| 20090283812 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF An object is to suppress reading error even in the case where writing and erasing are repeatedly performed. Further, another object is to reduce writing voltage and erasing voltage while increase in the area of a memory transistor is suppressed. A floating gate and a co... | 11/19/2009 |
| 20090286370 | Multi-State Non-Volatile Integrated Circuit Memory Systems that Employ Dielectric Storage Elements Non-volatile memory cells store a level of charge corresponding to the data being stored in a dielectric material storage element that is sandwiched between a control gate and the semiconductor substrate surface over channel regions of the memory cells. More than two me... | 11/19/2009 |
| 20090286369 | Method of manufacturing a semiconductor device In a method of manufacturing a semiconductor device, a tunnel insulation layer is formed on a substrate. A charge trapping layer is formed on the tunnel insulation layer. A protection layer pattern or a mold is formed on the charge trapping layer. Charge trapping layer ... | 11/19/2009 |
| 20090256191 | SPLIT GATE NON-VOLATILE MEMORY CELL WITH IMPROVED ENDURANCE AND METHOD THEREFOR A non-volatile memory cell including a substrate in which is formed a source region and a drain region defining a channel region between the source region and the drain region is provided. The non-volatile memory cell further includes a select gate structure overlying a... | 10/15/2009 |
| 20090251967 | NON-VOLATILE STORAGE HAVING A CONNECTED SOURCE AND WELL A non-volatile storage device is disclosed that includes a set of connected non-volatile storage elements formed on a well, a bit line contact positioned in the well, a source line contact positioned in the well, a bit line that is connected to the bit line contact, and... | 10/08/2009 |
| 20090212341 | SEMITUBULAR METAL-OXIDE-SEMICONDUCTOR FIELD EFFECT TRANSISTOR An epitaxial semiconductor layer or a stack of a silicon germanium alloy layer and an epitaxial strained silicon layer is formed on outer sidewalls of a porous silicon portion on a substrate. The porous silicon portion and any silicon germanium alloy material are remove... | 08/27/2009 |
| 20090148990 | Semiconductor devices and methods of forming the same A method of forming a semiconductor device includes forming line patterns on a substrate, the line patterns defining narrow and wide gap regions, forming spacer patterns in the narrow and wide gap regions on sidewalls of the line patterns, spacer patterns in the wide ga... | 06/11/2009 |
| 20090140315 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME A semiconductor memory device comprises: a plurality of transistors having a stacked-gate structure, each transistor including a semiconductor substrate, a gate insulator formed on the semiconductor substrate, a lower gate formed on the semiconductor substrate with the ... | 06/04/2009 |
| 20090121274 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME A salicide treatment is performed on a common source line to reduce surface resistance and contact resistance, thereby improving a cell current characteristic. Therefore, a chip can be reduced in size and chips per wafer can be increased, thereby achieving high yield. I... | 05/14/2009 |
| 20090101962 | Semiconductor devices and methods of manufacturing and operating same A semiconductor device and methods of manufacturing and operating the semiconductor device may be disclosed. The semiconductor device may comprise different nanostructures. The semiconductor device may have a first element formed of nanowires and a second element formed... | 04/23/2009 |
| 20090061582 | MANUFACTURING METHOD OF NON-VOLATILE MEMORY A manufacturing method of a non-volatile memory includes first providing a substrate for defining multiple pairs of active regions; forming a control gate in one of each pair of the active regions of the substrate; sequentially forming a gate oxide layer, a conductor la... | 03/05/2009 |
| 20090039420 | FINFET MEMORY CELL HAVING A FLOATING GATE AND METHOD THEREFOR A fin field effect transistor (FinFET) memory cell and method of formation has a substrate for providing mechanical support. A first dielectric layer overlies the substrate. A fin structure overlies the dielectric layer and has a first current electrode and a second cur... | 02/12/2009 |
| 20090035907 | METHOD OF FORMING STACKED GATE STRUCTURE FOR SEMICONDUCTOR MEMORY A method of manufacturing a nonvolatile semiconductor memory comprising: forming a gate insulating film formed on a surface of a semiconductor substrate; forming a source region and a drain region in the semiconductor substrate; forming a floating gate electrode on the ... | 02/05/2009 |
| 20090001447 | SEMICONDUCTOR DEVICE WITH DUMMY ELECTRODE A semiconductor device includes a gate electrode having a straight portion, a dummy electrode located at a point on the extension of the straight portion, a stopper insulating film, a sidewall insulating film, an interlayer insulating film, and a linear contact portion ... | 01/01/2009 |
| 20080303067 | SPLIT GATE MEMORY CELL USING SIDEWALL SPACERS A self-aligned split gate bitcell includes first and second regions of charge storage material separated by a gap devoid of charge storage material. Spacers are formed along sidewalls of sacrificial layer extending above and on opposite sides of the bitcell stack, where... | 12/11/2008 |
