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| Application No. | Application Title | Issue Date |
| 20120049262 | A DRAM CELL STRUCTURE WITH EXTENDED TRENCH AND A MANUFACTURING METHOD THEREOF A DRAM cell structure with extended trench, the DRAM cell structure comprises: a NMOS transistor and a trench capacitor connected with the source electrode of the NMOS transistor; the trench capacitor comprises: a semiconductor substrate; a multilayer structure as the b... | 03/01/2012 |
| 20120040504 | METHOD FOR INTEGRATING DRAM AND NVM The present invention discloses a method for integrating DRAM and NVM, which comprises steps: sequentially forming on a portion of surface of a DRAM semiconductor substrate a first gate insulation layer and a first gate layer functioning as a floating gate; and implanti... | 02/16/2012 |
| 20120025288 | SOI Trench DRAM Structure With Backside Strap In one exemplary embodiment, a semiconductor structure including: a silicon-on-insulator substrate having of a top silicon layer overlying an insulation layer, where the insulation layer overlies a bottom silicon layer; a capacitor disposed at least partially in the ins... | 02/02/2012 |
| 20120012913 | SEMICONDUCTOR DEVICE INCLUDING VERTICAL TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME A semiconductor device including a vertical transistor and a method for manufacturing the same may reduce a cell area in comparison with a conventional layout of 8F2 and 6F2. Also, the method does not require forming a bit line contact, a storage node contact or a landi... | 01/19/2012 |
| 20110284941 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE A semiconductor device includes: a transistor including source and drain diffusion-layers, a gate insulating film and a gate electrode; first and second plugs formed in a first interlayer-insulating film and connected to the source and drain diffusion-layers, respective... | 11/24/2011 |
| 20110272702 | ENHANCED CAPACITANCE DEEP TRENCH CAPACITOR FOR EDRAM A substrate including a stack of a handle substrate, an optional lower insulator layer, a doped polycrystalline semiconductor layer, an upper insulator layer, and a top semiconductor layer is provided. A deep trench is formed through the top semiconductor layer, the upp... | 11/10/2011 |
| 20110241093 | SEMICONDUCTOR DEVICE AND METHOD OF MAKING THE SAME A dual channel transistor includes a semiconductor island isolated by a first shallow trench isolation (STI) extending along a first direction and a second STI extending along a second direction, wherein the first direction intersect the second direction. The dual chann... | 10/06/2011 |
| 20110201161 | METHOD OF FORMING A BURIED PLATE BY ION IMPLANTATION A mask layer formed over a semiconductor substrate is lithographically patterned to form an opening therein. Ions are implanted at an angle that is normal to the surface of the semiconductor substrate through the opening and into an upper portion of the semiconductor su... | 08/18/2011 |
| 20110169131 | DEEP TRENCH DECOUPLING CAPACITOR Solutions for forming a silicided deep trench decoupling capacitor are disclosed. In one aspect, a semiconductor structure includes a trench capacitor within a silicon substrate, the trench capacitor including: an outer trench extending into the silicon substrate; a die... | 07/14/2011 |
| 20110133310 | INTEGRATED CIRCUIT AND A METHOD USING INTEGRATED PROCESS STEPS TO FORM DEEP TRENCH ISOLATION STRUCTURES AND DEEP TRENCH CAPACITOR STRUCTURES FOR THE INTEGRATED CIRCUIT Disclosed is an integrated circuit having at least one deep trench isolation structure and a deep trench capacitor. A method of forming the integrated circuit incorporates a single etch process to simultaneously form first trench(s) and a second trenches for the deep tr... | 06/09/2011 |
| 20110101435 | BURIED BIT LINE PROCESS AND SCHEME The embodiment provides a buried bit line process and scheme. The buried bit line is disposed in a trench formed in a substrate. The buried bit line includes a diffusion region formed in a portion of the substrate adjacent the trench. A blocking layer is formed on a por... | 05/05/2011 |
| 20110001175 | SEMICONDUCTOR MEMORY DEVICE AND FABRICATION METHOD THEREOF The present invention relates to a highly integrated semiconductor device in which a capacitor is formed between adjacent gate patterns by using a nanotube process. A semiconductor memory device according to an example embodiment of the present invention includes a capa... | 01/06/2011 |
| 20100304539 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE A method for manufacturing a semiconductor device includes preparing a semiconductor substrate having a first region of a first electrical conduction type as a part of a surface layer of the semiconductor substrate and a first gate electrode and a capacitor structure, t... | 12/02/2010 |
| 20100252873 | TRENCH STRUCTURE AND METHOD OF FORMING THE TRENCH STRUCTURE Disclosed are embodiments of an improved deep trench capacitor structure and memory device that incorporates this deep trench capacitor structure. The deep trench capacitor and memory device embodiments are formed on a semiconductor-on-insulator (SOI) wafer such that th... | 10/07/2010 |
| 20100240191 | METHOD OF FORMING SEMICONDUCTOR DEVICE HAVING A CAPACITOR A method of forming a semiconductor device includes forming a lower electrode layer on a substrate, forming a surface oxide layer on the lower electrode layer, partially removing the lower electrode layer to form a lower electrode, removing the surface oxide layer to ex... | 09/23/2010 |
| 20100203693 | MANUFACTURING METHOD OF DYNAMIC RANDOM ACCESS MEMORY A manufacturing method of DRAM is provided. A substrate having a deep trench is provided, and then a deep trench capacitor including a bottom electrode, an upper electrode and a capacitor dielectric layer is formed in the deep trench. A part of the upper electrode of th... | 08/12/2010 |
| 20100193852 | EMBEDDED DRAM MEMORY CELL WITH ADDITIONAL PATTERNING LAYER FOR IMPROVED STRAP FORMATION The present invention relates to semiconductor devices, and more particularly to a structure and method for forming memory cells in a semiconductor device using a patterning layer and etch sequence. The method includes forming trenches in a layered semiconductor structu... | 08/05/2010 |
| 20100155801 | Integrated circuit, 1T-1C embedded memory cell containing same, and method of manufacturing 1T-1C memory cell for embedded memory application An integrated circuit includes a semiconducting substrate (110), electrically conductive layers (120) over the semiconducting substrate, and a capacitor (130) at least partially embedded within the semiconducting substrate such that the capacitor is... | 06/24/2010 |
| 20100144106 | DYNAMIC RANDOM ACCESS MEMORY (DRAM) CELLS AND METHODS FOR FABRICATING THE SAME A method for fabricating a memory cell is provided. A trench is formed in a semiconductor structure that comprises a semiconductor layer, and a trench capacitor is formed in the trench. Conductivity determining impurities are implanted into the semiconductor structure t... | 06/10/2010 |
| 20100124806 | Methods of fabricating semiconductor devices A semiconductor device includes a semiconductor substrate that includes first and second regions; first, second, and third insulating layers; a capacitor dielectric layer that includes first and second dielectric layers; a gate insulating layer formed on the first and s... | 05/20/2010 |
| 20100052026 | DEEP TRENCH CAPACITOR FOR SOI CMOS DEVICES FOR SOFT ERROR IMMUNITY A semiconductor structure is disclosed. The semiconductor structure includes an active semiconductor layer, a semiconductor device having a gate disposed on top of the active semiconductor layer, and source and drain regions and a body/channel region disposed within the... | 03/04/2010 |
| 20100041191 | SPLIT-GATE DRAM WITH MUGFET, DESIGN STRUCTURE, AND METHOD OF MANUFACTURE A method of manufacturing a dynamic random access memory cell includes: forming a substrate having an insulating region over a conductive region; forming a fin of a fin-type field effect transistor (FinFET) device over the insulating region; forming a storage capacitor ... | 02/18/2010 |
| 20100032742 | INTEGRATED CIRCUITS COMPRISING AN ACTIVE TRANSISTOR ELECTRICALLY CONNECTED TO A TRENCH CAPACITOR BY AN OVERLYING CONTACT AND METHODS OF MAKING A method of forming an integrated circuit comprises: providing a semiconductor topography comprising an active transistor laterally adjacent to a trench capacitor formed in a semiconductor substrate, the active transistor comprising a source junction and a drain junctio... | 02/11/2010 |
| 20100006913 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME A semiconductor device includes: a semiconductor substrate including a trench; a capacitor electrode formed in the trench; a first insulation film formed on a bottom of the trench and between the semiconductor substrate and the capacitor electrode; a second insulation f... | 01/14/2010 |
| 20090256185 | METALLIZED CONDUCTIVE STRAP SPACER FOR SOI DEEP TRENCH CAPACITOR A conductive strap spacer is formed within a buried strap cavity above an inner electrode recessed below a top surface of a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A portion of the conductive strap spacer is metallized by reacting with a ... | 10/15/2009 |
| 20090250738 | SIMULTANEOUS BURIED STRAP AND BURIED CONTACT VIA FORMATION FOR SOI DEEP TRENCH CAPACITOR A node dielectric, an inner electrode, and a buried strap cavity are formed in the deep trench in an SOI substrate. A buried layer contact cavity is formed by lithographic methods. The buried strap cavity and the buried layer contact cavity are filled simultaneously by ... | 10/08/2009 |
| 20090224304 | SOFT ERROR PROTECTION STRUCTURE EMPLOYING A DEEP TRENCH A deep trench containing a doped semiconductor fill portion having a first conductivity type doping and surrounded by a buried plate layer having a second conductivity type doping at a lower portion is formed in a semiconductor layer having a doping of the first conduct... | 09/10/2009 |
| 20090173980 | PROVIDING ISOLATION FOR WORDLINE PASSING OVER DEEP TRENCH CAPACITOR A memory cell has an access transistor and a capacitor with an electrode disposed within a deep trench. STI oxide covers at least a portion of the electrode, and a liner covers a remaining portion of the electrode. The liner may be a layer of nitride over a layer of oxi... | 07/09/2009 |
| 20090166701 | One transistor/one capacitor dynamic random access memory (1T/1C DRAM) cell In general, in one aspect, a method includes forming a semiconductor fin. A first insulating layer is formed adjacent to the semiconductor fin. A second insulating layer is formed over the first insulating layer and the semiconductor fin. A first trench is formed in the... | 07/02/2009 |
| 20090134442 | RECESSED CHANNEL DEVICE AND METHOD THEREOF A method for forming a recessed channel device includes providing a substrate with a plurality of trench capacitors formed therein, each of the trench capacitors including a plug protruding above the substrate; forming a spacer on each of the plugs; forming a plurality ... | 05/28/2009 |
| 20090130807 | Trench DRAM Cell with Vertical Device and Buried Word Lines A DRAM array having trench capacitor cells of potentially 4F2 surface area (F being the photolithographic minimum feature width), and a process for fabricating such an array. The array has a cross-point cell layout in which a memory cell is located at the int... | 05/21/2009 |
| 20090121269 | INTEGRATED CIRCUIT COMPRISING A TRANSISTOR AND A CAPACITOR, AND FABRICATION METHOD An integrated circuit includes a substrate and at least one active region. A transistor produced in the active region separated from the substrate. This transistor includes a source or drain first region and a drain or source second region which are connected by a chann... | 05/14/2009 |
| 20090101956 | EMBEDDED TRENCH CAPACITOR HAVING A HIGH-K NODE DIELECTRIC AND A METALLIC INNER ELECTRODE A deep trench is formed in a semiconductor substrate and a pad layer thereupon, and filled with a dummy node dielectric and a dummy trench fill. A shallow trench isolation structure is formed in the semiconductor substrate. A dummy gate structure is formed in a device r... | 04/23/2009 |
| 20090098698 | MEMORY DEVICE AND FABRICATION THEREOF A semiconductor memory device. A trench capacitor disposed at a lower portion of a trench in a substrate, in which the trench capacitor comprises a filling electrode layer and a collar dielectric layer surrounding the filling electrode layer. The top of the collar diele... | 04/16/2009 |
| 20090090950 | SEMICONDUCTOR DEVICES Methods, devices, modules, and systems providing semiconductor devices in a stacked wafer system are described herein. One embodiment includes a first wafer for NMOS transistors in a CMOS architecture and a second wafer for PMOS transistors in the CMOS architecture, wit... | 04/09/2009 |
| 20090057740 | Memory with surface strap A memory with a surface strap. The memory comprises a trench capacitor, a self-aligned surface strap and a MOS transistor. The trench capacitor is formed in a semiconductor substrate. The self-aligned surface strap covers an opening of the trench capacitor and a active ... | 03/05/2009 |
| 20090061580 | METHOD OF FORMING FINFET DEVICE The invention discloses a method of forming a finFET device. A hard mask layer is formed on an active area of a semiconductor substrate. A portion of the hard mask layer is etched to form a recess. A conformal gate defining layer is deposited on the recess and a tilt an... | 03/05/2009 |
| 20090035901 | METHOD FOR FABRICATING MEMORY DEVICE WITH RECESS CHANNEL MOS TRANSISTOR A method for fabricating line type recess channel MOS transistors utilizes a lithography process to form line type gate trenches in the line type recess channel MOS transistors before finishing a STI process. The method can further control the critical dimension variati... | 02/05/2009 |
| 20090026516 | SEMICONDUCTOR MEMORY DEVICE AND FABRICATION METHOD THEREOF A method for fabricating a semiconductor memory device. A pair of neighboring trench capacitors is formed in a substrate. An insulating layer having a pair of connecting structures therein is formed on the substrate, in which the pair of connecting structures is electri... | 01/29/2009 |
| 20080318377 | METHOD OF FORMING SELF-ALIGNED GATES AND TRANSISTORS Method for fabricating a self-aligned gate of a transistor including: forming a plurality of deep trench capacitors in a substrate, concurrently forming a surface strap and a contact pad on a surface of the substrate, wherein a spacing between the surface strap and the ... | 12/25/2008 |
