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Class 438/231 - Plural doping steps


Subclass of Class 438 - Semiconductor device manufacturing: process
Definition: Process including multiple steps of introducing electrically
No. of applications: 130
Last issue date: 05/03/2012


1        
Application No.Application TitleIssue Date
20120108021PMOS SiGe-LAST INTEGRATION PROCESS
A process of forming a CMOS integrated circuit including integrating SiGe source/drains in the PMOS transistor after source/drain and LDD implants and anneals. A dual layer hard mask is formed on a polysilicon gate layer. The bottom layer prevents SiGe growth on the pol... 		05/03/2012
20120104510CMOS PROCESS TO IMPROVE SRAM YIELD
An integrated circuit containing an SAR SRAM and CMOS logic, in which sidewall spacers on the gate extension of the SAR SRAM cell are thinner than sidewall spacers on the logic PMOS gates, so that the depth of the drain node SRAM PSD layer is maintained under the stretc... 		05/03/2012
20120080757SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
First protective films are formed to cover side surfaces of gate electrode portions. In an nMOS region, an extention implantation region is formed by causing a portion of the first protective film located on the side surface of the gate electrode portion to function as ... 		04/05/2012
20120049201SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME
In a CMIS device, to improve the operating characteristics of an n-channel electric field transistor that is formed by using a strained silicon technique, without degrading the operating characteristics of a p-channel field effect transistor. After forming a source/drai... 		03/01/2012
20120045876METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE
There is provided a technology capable of preventing the increase in threshold voltages of n channel type MISFETs and p channel type MISFETs in a semiconductor device including CMISFETs having high dielectric constant gate insulation films and metal gate electrodes. Whe... 		02/23/2012
20120012938METHOD OF MANUFACTURING COMPLEMENTARY METAL OXIDE SEMICONDUCTOR DEVICE
A method of manufacturing a CMOS device includes providing a substrate having a first region and a second region; forming a first gate structure and a second gate structure, each of the gate structures comprising a sacrificial layer and a hard mask layer; forming a patt... 		01/19/2012
20120015490METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES
A method of manufacturing a semiconductor device includes forming a gate structure on a substrate; forming a sacrificial spacer may be formed on a sidewall of the gate substrate; implanting first impurities into portions of the substrate by a first ion implantation proc... 		01/19/2012
20110256676Methods of Manufacturing a Semiconductor Device
Methods of manufacturing a semiconductor device include forming integrated structures of polysilicon patterns and hard mask patterns on a substrate divided into at least an NMOS forming region and a PMOS forming region. A first preliminary insulating interlayer is forme... 		10/20/2011
20110237036MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
By ion-implanting an inert gas, for example, nitrogen into a polycrystalline silicon film in an nMIS forming region from an upper surface of the polycrystalline silicon film down to a predetermined depth, an upper portion of the polycrystalline silicon film is converted... 		09/29/2011
20110215412STRUCTURE AND METHOD TO FABRICATE pFETS WITH SUPERIOR GIDL BY LOCALIZING WORKFUNCTION
A semiconductor structure and a method of forming the same are provided in which the gate induced drain leakage is controlled by introducing a workfunction tuning species within selected portions of a pFET such that the gate/SD (source/drain) overlap area of the pFET is... 		09/08/2011
20110207273Methods of Manufacturing Transistors
A transistor includes a silicon germanium channel layer formed on a portion of a single crystalline silicon substrate. The silicon germanium channel layer includes a Si—H bond and/or a Ge—H bond at an inner portion or an upper surface portion thereof. A PMOS transis... 		08/25/2011
20110201166METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES
A method of manufacturing a semiconductor device includes forming a gate electrode on a semiconductor substrate and a sidewall spacer on the gate electrode. Then, a portion of the semiconductor substrate at both sides of the sidewall spacer is partially etched to form a... 		08/18/2011
20110198707SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD
A semiconductor device manufacturing method includes, forming isolation region having an aspect ratio of 1 or more in a semiconductor substrate, forming a gate insulating film, forming a silicon gate electrode and a silicon resistive element, forming side wall spacers o... 		08/18/2011
20110171794TRANSISTOR FORMATION USING CAPPING LAYER
A method of transistor formation using a capping layer in complimentary metal-oxide semiconductor (CMOS) structures is provided, the method including: depositing a conductive layer over an n-type field effect transistor (nFET) and over a p-type field effect transistor (... 		07/14/2011
20110133288TRANSISTOR OF SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
A method of fabricating a transistor of a semiconductor device comprises: forming a gate in a NMOS region and a PMOS region of a semiconductor substrate; forming a gate spacer on a sidewall of the gate; performing an ion implantation process on the NMOS region to form a... 		06/09/2011
20110136307SEMICONDUCTOR DEVICE HAVING BUFFER LAYER BETWEEN SIDEWALL INSULATING FILM AND SEMICONDUCTOR SUBSTRATE
A semiconductor device includes an NMOS transistor and a PMOS transistor. The NMOS transistor includes a channel area formed in a silicon substrate, a gate electrode formed on a gate insulating film in correspondence with the channel area, and a source area and a drain ... 		06/09/2011
20110127617PERFORMANCE ENHANCEMENT IN TRANSISTORS COMPRISING HIGH-K METAL GATE STACK BY AN EARLY EXTENSION IMPLANTATION
In sophisticated transistor elements, integrity of sensitive gate materials may be enhanced while, at the same time, the lateral offset of extension regions may be reduced. To this end, at least a portion of the extension regions may be implanted at an early manufacturi... 		06/02/2011
20110129972TRANSISTOR INCLUDING A HIGH-K METAL GATE ELECTRODE STRUCTURE FORMED ON THE BASIS OF A SIMPLIFIED SPACER REGIME
In sophisticated semiconductor devices, the threshold voltage adjustment of high-k metal gate electrode structures may be accomplished by a work function metal species provided in an early manufacturing stage. For this purpose, a protective sidewall spacer structure is ... 		06/02/2011
20110121398TECHNIQUE FOR ENHANCING DOPANT PROFILE AND CHANNEL CONDUCTIVITY BY MILLISECOND ANNEAL PROCESSES
During the fabrication of advanced transistors, significant dopant diffusion may be suppressed by performing a millisecond anneal process after completing the basic transistor configuration, wherein a stress memorization technique may also be obtained by forming a strai... 		05/26/2011
20110117709SEMICONDUCTOR DEVICE FABRICATING METHOD
A semiconductor device fabricating method is described. The semiconductor device fabricating method includes providing a substrate. A first gate insulating layer and a second gate insulating layer are formed on the substrate, respectively. A gate layer is blanketly form... 		05/19/2011
20110070703Disposable Spacer Integration with Stress Memorization Technique and Silicon-Germanium
An integrated process flow for forming an NMOS transistor (104) and an embedded SiGe (eSiGe) PMOS transistor (102) using a stress memorization technique (SMT) layer (126). The SMT layer (126) is deposited over both the NMOS transistor (104... 		03/24/2011
20110059584MANUFACTURING PROCESS OF FIN-TYPE FIELD EFFECT TRANSISTOR AND SEMICONDUCTOR
A constant distance can be maintained between source/drain regions without providing a gate side wall by forming a gate electrode including an eaves structure, and a uniform dopant concentration is kept within a semiconductor by ion implantation. As a result, a FinFET e... 		03/10/2011
20110049643SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
According to one embodiment, a method of manufacturing a semiconductor device including forming a gate structure includes a metal gate electrode on a semiconductor substrate, forming two first sidewalls of an insulating material on both side surfaces of the gate structu... 		03/03/2011
20110042729METHOD FOR IMPROVING SELECTIVITY OF EPI PROCESS
The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming a gate structure over the substrate, forming a material layer over the substrate and the gate structure, implanting Ge, C, P, F, or ... 		02/24/2011
20110027952FORMATION OF A CHANNEL SEMICONDUCTOR ALLOY BY DEPOSITING A HARD MASK FOR THE SELECTIVE EPITAXIAL GROWTH
A growth mask provided for the deposition of a threshold adjusting semiconductor alloy may be formed on the basis of a deposition process, thereby obtaining superior thickness uniformity. Consequently, P-channel transistors and N-channel transistors with an advanced hig... 		02/03/2011
20110012197METHOD OF FABRICATING TRANSISTORS AND A TRANSISTOR STRUCTURE FOR IMPROVING SHORT CHANNEL EFFECT AND DRAIN INDUCED BARRIER LOWERING
A method of fabricating transistors includes: providing a substrate including an N-type well and P-type well; forming a first gate on the N-type well and a second gate on the P-type well, respectively; forming a third spacer on the first gate; forming an epitaxial layer... 		01/20/2011
20110003445MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
A manufacturing method of a semiconductor device is provided which can uniformly form a good and thin silicon oxide film or the like at a relatively low temperature. In step 1, a semiconductor substrate is exposed to monosilane (SiH4). Then, in step 		01/06/2011
20100285641MASK ROM DEVICE, SEMICONDUCTOR DEVICE INCLUDING THE MASK ROM DEVICE, AND METHODS OF FABRICATING MASK ROM DEVICE AND SEMICONDUCTOR DEVICE
A mask read-only memory (ROM) device, which can stably output data, includes an on-cell and an off-cell. The on-cell includes an on-cell gate structure on a substrate and an on-cell junction structure within the substrate. The off-cell includes an off-cell gate structur... 		11/11/2010
20100237431REDUCING TRANSISTOR JUNCTION CAPACITANCE BY RECESSING DRAIN AND SOURCE REGIONS
By recessing portions of the drain and source areas on the basis of a spacer structure, the subsequent implantation process for forming the deep drain and source regions may result in a moderately high dopant concentration extending down to the buried insulating layer o... 		09/23/2010
20100233861METHOD FOR MANUFACTURING SOLID-STATE IMAGING DEVICE
A method is provided for manufacturing a solid-state imaging device including a semiconductor substrate having a photoelectric conversion portion, a pixel transistor region and a logic circuit region. The method includes the steps of forming a first gate electrode on th... 		09/16/2010
20100224937METHOD FOR INTEGRATING SILICON GERMANIUM AND CARBON DOPED SILICON WITHIN A STRAINED CMOS FLOW
The disclosure provides a semiconductor device and method of manufacture therefore. The method for manufacturing the semiconductor device, in one embodiment, includes providing a substrate (210) having a PMOS device region (220) and NMOS device region (... 		09/09/2010
20100216288Fabrication of Source/Drain Extensions with Ultra-Shallow Junctions
A method of forming an integrated circuit device includes providing a semiconductor substrate; forming a gate structure on the semiconductor substrate; and performing a pre-amorphized implantation (PAI) by implanting a first element selected from a group consisting esse... 		08/26/2010
20100197093STRESS OPTIMIZATION IN DUAL EMBEDDED EPITAXIALLY GROWN SEMICONDUCTOR PROCESSING
A method of manufacturing dual embedded epitaxially grown semiconductor transistors is provided, the method including depositing a first elongated oxide spacer over first and second transistors of different types, depositing a first elongated nitride spacer on the first... 		08/05/2010
20100084712MULTIPLE SPACER AND CARBON IMPLANT COMPRISING PROCESS AND SEMICONDUCTOR DEVICES THEREFROM
An integrated circuit (IC) and multi-spacer methods for forming the same includes at least one metal-oxide semiconductor (MOS) transistor including a substrate having a semiconductor surface, a gate stack formed in or on the surface comprising a gate electrode on a gate... 		04/08/2010
20100078654SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
A semiconductor device according to one embodiment includes: a first transistor comprising a first gate electrode formed on a semiconductor substrate via a first gate insulating film, a first channel region formed in the semiconductor substrate under the first gate insu... 		04/01/2010
20100065916SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
Disclosed are a semiconductor device and a method for manufacturing the same. The semiconductor device includes an isolation area formed on a semiconductor substrate to define NMOS and PMOS areas, a gate insulating layer and a gate formed on each of the NMOS and PMOS ar... 		03/18/2010
20100065910SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor device includes a first MISFET and a second MISFET, wherein the first MISFET includes a semiconductor substrate 100, a first gate insulating film 101a and a first gate electrode 102a formed on the first region of the se... 		03/18/2010
20100062576METHOD FOR FABRICATING CMOS IMAGE SENSOR WITH PLASMA DAMAGE-FREE PHOTODIODE
A method for fabricating a complementary metal-oxide semiconductor (CMOS) image sensor includes providing a semi-finished substrate, forming a patterned blocking layer over a photodiode region of the substrate, implanting impurities on regions other than the photodiode ... 		03/11/2010
20100019324MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
By ion-implanting an inert gas, for example, nitrogen into a polycrystalline silicon film in an nMIS forming region from an upper surface of the polycrystalline silicon film down to a predetermined depth, an upper portion of the polycrystalline silicon film is converted... 		01/28/2010
20090294866Transistor Fabrication Methods and Structures Thereof
Methods of fabricating transistors and semiconductor devices and structures thereof are disclosed. In one embodiment, a method of fabricating a transistor includes forming a gate dielectric over a workpiece, forming a gate over the gate dielectric, and forming a stress-... 		12/03/2009
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