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| Application No. | Application Title | Issue Date |
| 20120104470 | REPLACEMENT GATE MOSFET WITH RAISED SOURCE AND DRAIN A disposable dielectric spacer is formed on sidewalls of a disposable material stack. Raised source/drain regions are formed on planar source/drain regions by selective epitaxy. The disposable dielectric spacer is removed to expose portions of a semiconductor layer betw... | 05/03/2012 |
| 20120104397 | ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME Provided are an organic light emitting display device and a method of manufacturing the same. The organic light emitting display device includes a thin-film transistor (TFT), which includes an active layer, a gate electrode, and source/drain electrodes; an organic elect... | 05/03/2012 |
| 20120104495 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME The present application discloses a semiconductor structure and a method for manufacturing the same. The semiconductor structure according to the present invention adjusts a threshold voltage with a common contact, which has a portion outside the source or drain region ... | 05/03/2012 |
| 20120080658 | Graphene electronic device and method of fabricating the same A graphene electronic device and a method of fabricating the graphene electronic device are provided. The graphene electronic device may include a graphene channel layer formed on a hydrophobic polymer layer, and a passivation layer formed on the graphene channel layer.... | 04/05/2012 |
| 20120083076 | Ultra-Shallow Junction MOSFET Having a High-k Gate Dielectric and In-Situ Doped Selective Epitaxy Source/Drain Extensions and a Method of Making Same A MOSFET includes a gate having a high-k gate dielectric on a substrate and a gate electrode on the gate dielectric. The gate dielectric protrudes beyond the gate electrode. A deep source and drain having shallow extensions are formed on either side of the gate. The dee... | 04/05/2012 |
| 20120080753 | GALLIUM ARSENIDE BASED MATERIALS USED IN THIN FILM TRANSISTOR APPLICATIONS Embodiments of the invention provide a method of forming a group III-V material utilized in thin film transistor devices. In one embodiment, a gallium arsenide based (GaAs) layer with or without dopants formed from a solution based precursor may be utilized in thin film... | 04/05/2012 |
| 20120068264 | FORMING NARROW FINS FOR FINFET DEVICES USING ASYMMETRICALLY SPACED MANDRELS A method of forming fins for fin-shaped field effect transistor (finFET) devices includes forming a plurality of sacrificial mandrels over a semiconductor substrate. The plurality of sacrificial mandrels are spaced apart from one another by a first distance along a firs... | 03/22/2012 |
| 20120068150 | Nanowire Field Effect Transistors A method for forming a nanowire field effect transistor (FET) device including forming a first silicon on insulator (SOI) pad region, a second SOI pad region, a third SOI pad region, a first SOI portion connecting the first SOI pad region to the second SOI pad region, a... | 03/22/2012 |
| 20120052635 | CONDUCTIVE LAYER BURIED-TYPE SUBSTRATE, METHOD OF FORMING THE CONDUCTIVE LAYER BURIED-TYPE SUBSTRATE, AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING THE CONDUCTIVE LAYER BURIED-TYPE SUBSTRATE A conductive layer buried-type substrate is disclosed. The substrate includes a silicon oxidation layer bonded to a supporting substrate, an adhesion promotion layer that is formed on the silicon oxidation layer and improves an adhesion between the silicon oxidation lay... | 03/01/2012 |
| 20120052636 | METHOD OF MANUFACTURING THIN FILM TRANSISTOR A thin film transistor includes a gate electrode, a first insulating layer on the gate electrode, a semiconductor layer on the gate electrode and separated from the gate electrode by the first insulating layer, the semiconductor layer including a channel region correspo... | 03/01/2012 |
| 20120043580 | Semiconductor Device and Manufacturing Method Thereof There are provided a structure of a semiconductor device in which low power consumption is realized even in a case where a size of a display region is increased to be a large size screen and a manufacturing method thereof. A gate electrode in a pixel portion is formed a... | 02/23/2012 |
| 20120043545 | THIN FILM TRANSISTOR DISPLAY PANEL AND MANUFACTURING METHOD THEREOF A thin film transistor display panel includes a substrate, a gate wire on the substrate and including a gate line and a gate electrode; a gate insulating layer on the gate wire; a semiconductor layer on the gate insulating layer; a data wire including a source electrode... | 02/23/2012 |
| 20120037991 | Silicon on Insulator Field Effect Device A field effect transistor device includes a silicon on insulator (SOI) body portion disposed on a buried oxide (BOX) substrate, a gate stack portion disposed on the SOI body portion, a first silicide material disposed on the BOX substrate arranged adjacent to the gate s... | 02/16/2012 |
| 20120032262 | ENHANCED HVPMOS A p-channel LDMOS device with a controlled n-type buried layer (NBL) is disclosed. A Shallow Trench Isolation (STI) oxidation is defined, partially or totally covering the drift region length. The NBL layer, which can be defined with the p-well mask, connects to the n-w... | 02/09/2012 |
| 20120025312 | Strain Engineering in Three-Dimensional Transistors Based on a Strained Channel Semiconductor Material In three-dimensional transistor configurations, such as finFETs, at least one surface of the semiconductor fin may be provided with a strained semiconductor material, which may thus have a pronounced uniaxial strain component along the current flow direction. The strain... | 02/02/2012 |
| 20120018809 | MOS DEVICE FOR ELIMINATING FLOATING BODY EFFECTS AND SELF-HEATING EFFECTS A MOS device having low floating charge and low self-heating effects are disclosed. The device includes a connective layer coupling the active gate channel to the Si substrate. The connective layer provides electrical and thermal passages during device operation, which ... | 01/26/2012 |
| 20120018727 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME An insulating layer which releases a large amount of oxygen is used as an insulating layer in contact with a channel region of an oxide semiconductor layer, and an insulating layer which releases a small amount of oxygen is used as an insulating layer in contact with a ... | 01/26/2012 |
| 20120018806 | SEMICONDUCTOR-ON-INSULATOR (SOI) STRUCTURE WITH SELECTIVELY PLACED SUB-INSULATOR LAYER VOID(S) AND METHOD OF FORMING THE SOI STRUCTURE Disclosed is a semiconductor-on-insulator (SOI) structure having sub-insulator layer void(s) selectively placed in a substrate so that capacitance coupling between a first section of a semiconductor layer and the substrate will be less than capacitance coupling between ... | 01/26/2012 |
| 20120012932 | FIN-LIKE FIELD EFFECT TRANSISTOR (FINFET) DEVICE AND METHOD OF MANUFACTURING SAME A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary FinFET device includes a semiconductor substrate; a fin structure disposed over the semiconductor substrate; and a gate structure disposed on a portion of the fin structure. The gate s... | 01/19/2012 |
| 20120012835 | Metal Oxide Semiconductor Thin Film Transistors A top gate and bottom gate thin film transistor (TFT) are provided with an associated fabrication method. The TFT is fabricated from a substrate, and an active metal oxide semiconductor (MOS) layer overlying the substrate. Source/drain (S/D) regions are formed in contac... | 01/19/2012 |
| 20120012931 | SOI MOS DEVICE HAVING BTS STRUCTURE AND MANUFACTURING METHOD THEREOF The present invention discloses a SOI MOS device having BTS structure and manufacturing method thereof. The source region of the SOI MOS device comprises: two heavily doped N-type regions, a heavily doped P-type region formed between the two heavily doped N-type regions... | 01/19/2012 |
| 20120007051 | Process for Forming a Surrounding Gate for a Nanowire Using a Sacrificial Patternable Dielectric Techniques for defining a damascene gate in nanowire FET devices are provided. In one aspect, a method of fabricating a FET device is provided including the following steps. A SOI wafer is provided having a SOI layer over a BOX. Nanowires and pads are patterned in the S... | 01/12/2012 |
| 20120007054 | Self-Aligned Contacts in Carbon Devices A method for forming a semiconductor device includes forming a carbon material on a substrate, forming a gate stack on the carbon material, removing a portion of the substrate to form at least one cavity defined by a portion of the carbon material and the substrate, and... | 01/12/2012 |
| 20120009740 | METHOD FOR FABRICATING SOI HIGH VOLTAGE POWER CHIP WITH TRENCHES A method of manufacturing a SOI high voltage power chip with trenches is disclosed. The method comprises: forming a cave and trenches at a SOI substrate; filling oxide in the cave; oxidizing the trenches, forming oxide isolation regions for separating low voltage device... | 01/12/2012 |
| 20120007180 | FinFET with novel body contact for multiple Vt applications FinFET devices are formed with body contact structures enabling the fabrication of such devices having different gate threshold voltages (Vt). A body contact layer is formed to contact the gate electrode (contact) enabling a forward body bias and a reduction in Vt. Two ... | 01/12/2012 |
| 20120007181 | Schottky FET Fabricated With Gate Last Process A method for forming a field effect transistor (FET) includes forming a dummy gate on a top semiconductor layer of a semiconductor on insulator substrate; forming source and drain regions in the top semiconductor layer, wherein the source and drain regions are located i... | 01/12/2012 |
| 20120001173 | FLEXIBLE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME There is provided a flexible semiconductor device. The flexible semiconductor device of the present invention comprising a support layer, a semiconductor structure portion formed on the support layer, and a resin film formed on the semiconductor structure portion. The r... | 01/05/2012 |
| 20120003797 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF When a transistor including a conductive layer having a three-layer structure is manufactured, three-stage etching is performed. In the first etching process, an etching method in which the etching rates for the second film and the third film are high is employed, and t... | 01/05/2012 |
| 20110315950 | NANOWIRE FET WITH TRAPEZOID GATE STRUCTURE In one embodiment, a method of providing a nanowire semiconductor device is provided, in which the gate structure to the nanowire semiconductor device has a trapezoid shape. The method may include forming a trapezoid gate structure surrounding at least a portion of a ci... | 12/29/2011 |
| 20110309333 | SEMICONDUCTOR DEVICES FABRICATED BY DOPED MATERIAL LAYER AS DOPANT SOURCE A method of forming a semiconductor device is provided, in which the dopant for the source and drain regions is introduced from a doped dielectric layer. In one example, a gate structure is formed on a semiconductor layer of an SOI substrate, in which the thickness of t... | 12/22/2011 |
| 20110309334 | Graphene/Nanostructure FET with Self-Aligned Contact and Gate A method for forming a field effect transistor (FET) includes depositing a channel material on a substrate, the channel material comprising one of graphene or a nanostructure; forming a gate over a first portion of the channel material; forming spacers adjacent to the g... | 12/22/2011 |
| 20110309332 | EPITAXIAL SOURCE/DRAIN CONTACTS SELF-ALIGNED TO GATES FOR DEPOSITED FET CHANNELS A method of forming a self-aligned device is provided and includes depositing carbon nanotubes (CNTs) onto a crystalline dielectric substrate, isolating a portion of the crystalline dielectric substrate encompassing a location of the CNTs, forming gate dielectric and ga... | 12/22/2011 |
| 20110306169 | CAPPING LAYERS FOR METAL OXYNITRIDE TFTS A capping layer may be deposited over the active channel of a thin film transistor (TFT) in order to protect the active channel from contamination. The capping layer may affect the performance of the TFT. If the capping layer contains too much hydrogen, nitrogen, or oxy... | 12/15/2011 |
| 20110303923 | TFT, ARRAY SUBSTRATE FOR DISPLAY APPARATUS INCLUDING TFT, AND METHODS OF MANUFACTURING TFT AND ARRAY SUBSTRATE A thin film transistor (TFT), an array substrate including the TFT, and methods of manufacturing the TFT and the array substrate. The TFT includes an active layer, and a metal member that corresponds to a portion of each of the source region and the drain region of the ... | 12/15/2011 |
| 20110303972 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME A semiconductor device manufacturing method of an embodiment includes the steps of: forming a first insulating layer on a semiconductor substrate; forming on the first insulating layer an amorphous or polycrystalline semiconductor layer having a narrow portion; forming ... | 12/15/2011 |
| 20110300674 | Method of crystallizing silicon layer and method of forming a thin film transistor using the same A method of crystallizing a silicon layer and a method of manufacturing a thin film transistor using the same, the method of crystallizing the silicon layer including forming an amorphous silicon layer on a substrate; performing a hydrophobicity treatment on a surface o... | 12/08/2011 |
| 20110300675 | Method of fabricating thin film transistor The thin film transistor for an organic light emitting diode includes a crystalline semiconductor pattern on a substrate, a gate insulating layer on the crystalline semiconductor pattern having first source and drain contact holes, a gate electrode on the gate insulatin... | 12/08/2011 |
| 20110300676 | Method for Providing Lateral Thermal Processing of Thin Films on Low-Temperature Substrates A method for thermally processing a minimally absorbing thin film in a selective manner is disclosed. Two closely spaced absorbing traces are patterned in thermal contact with the thin film. A pulsed radiant source is used to heat the two absorbing traces, and the thin ... | 12/08/2011 |
| 20110294257 | METHODS OF PROVIDING SEMICONDUCTOR LAYERS FROM AMIC ACID SALTS A semiconductor layer and device can be provided using a method including thermally converting an aromatic, non-polymeric amic acid salt to a corresponding arylene diimide. The semiconducting thin films can be used in various articles including thin-film transistor devi... | 12/01/2011 |
| 20110294266 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE Formation of LDD structures and GOLD structures in a semiconductor device is conventionally performed in a self aligning manner with gate electrodes as masks, but there are many cases in which the gate electrodes have two layer structures, and film formation processes a... | 12/01/2011 |
