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| Application No. | Application Title | Issue Date |
| 20120069944 | Frequency Synchronization Using Clock Recovery Loop with Adaptive Packet Filtering An endpoint or other communication device of a communication system includes a clock recovery loop having a phase error estimator. The communication device is operative as a slave device relative to another communication device that is operative as a master device. The ... | 03/22/2012 |
| 20120051480 | PHASE LOCKED LOOP, CDR CIRCUIT, AND RECEIVING CIRCUIT In a phase locked loop, frequency-divided clocks each of which is given a phase difference of at least one cycle of a feedback clock are inputted to a first phase comparator and a second phase comparator, respectively, which are made to perform phase comparison with a r... | 03/01/2012 |
| 20120008726 | DELAY LOCKED LOOP A delay locked loop includes a delay amount setting unit configured to set a delay amount of an external clock signal, a coarse delay unit configured to primarily delay the external clock signal by the set delay amount based on a first unit duration which is a unit dela... | 01/12/2012 |
| 20120008727 | WIDE BAND CLOCK DATA RECOVERY The present disclosure provides a clock data recovery circuit that includes a phase locked loop unit, a delay locked loop unit and digital clock data recovery unit. The phase locked loop unit generates a clock signal based on a reference signal. The delay locked loop un... | 01/12/2012 |
| 20110318021 | Feed-Forward Carrier Phase Recovery for Optical Communications The carrier phase of a carrier wave modulated with information symbols is recovered with a multi-stage, feed-forward carrier phase recovery method. A series of digital signals corresponding to the information signals is received. For each digital signal, a coarse phase ... | 12/29/2011 |
| 20110314321 | HIGH SPEED DIGITAL BIT STREAM AUTOMATIC RATE SENSE DETECTION As part of the protocol for Common Public Radio Interface/Open Base Station Architecture Initiative (CPRI/OBSAI) systems, multiple data rates are support, which are each supported by one or more reference clock frequencies. Traditionally, timing circuits present used fo... | 12/22/2011 |
| 20110310942 | HIGHLY FLEXIBLE FRACTIONAL N FREQUENCY SYNTHESIZER One embodiment of the present invention provides a phase-locked loop (PLL) for synthesizing a fractional frequency. The PLL can include a 1/N frequency divider, a voltage-controlled oscillator (VCO), a programmable phase mixer, and a phase detector. The programmable pha... | 12/22/2011 |
| 20110311012 | METHOD AND DATA TRANSCEIVING SYSTEM FOR GENERATING REFERENCE CLOCK SIGNAL A method and a data transceiving system for generating a reference clock signal are provided. The data transceiving system comprises a voltage controlled oscillator, a phase lock loop (PLL) unit, and a data receiver. The voltage controlled oscillator is used to generate... | 12/22/2011 |
| 20110299642 | NOISE SHAPED INTERPOLATOR AND DECIMATOR APPARATUS AND METHOD Improved interpolator and decimator apparatus and methods, including the addition of an elastic storage element in the signal path. In one exemplary embodiment, the elastic element comprises a FIFO which advantageously allows short term variation in sample clocks to be ... | 12/08/2011 |
| 20110299644 | Emission Suppression for Wireless Communication Devices A method may include synchronizing an output of a phase-locked loop to a signal received at its input. The method may further include suppressing emission at a potentially problematic channel by applying at least one of a first gain and a first resistance of the phase-l... | 12/08/2011 |
| 20110293055 | CIRCUIT FOR GENERATING A CLOCK DATA RECOVERY PHASE LOCKED INDICATOR AND METHOD THEREOF A circuit includes an oversampling logic unit, an alternating current estimator, and a logic processor. The oversampling logic unit generates a plurality of alternating current terms according to an oversampling clock, and outputs a plurality of alternating current term... | 12/01/2011 |
| 20110274143 | SPREAD SPECTRUM CLOCK SIGNAL GENERATOR METHOD AND SYSTEM A system and method for generating a spread spectrum clock signal with a constant ppm offset as a function of a repetition number. A phase interpolator can be configured in association with of a phase-locked loop circuit in order to provide a phase movement from a bit c... | 11/10/2011 |
| 20110243290 | PHASE-LOCKED LOOP A PLL circuit (1a, 1b) for generating a pixel-clock signal based on a hsync signal. The PLL circuit comprises a phase-frequency detector arranged to receive the hsync signal and a frequency divided pixel-clock signal, and generate up and down... | 10/06/2011 |
| 20110243291 | SYNCHRONOUS TRANSFER OF STREAMING DATA IN A DISTRIBUTED ANTENNA SYSTEM Embodiments of the invention provide a method, distributed antenna system, and components that generate a jitter reduced clock signal from a serial encoded binary data stream transmitted over a communication medium. The method comprises receiving a modulated signal that... | 10/06/2011 |
| 20110228889 | Repeater Architecture with Single Clock Multiplier Unit A circuit for clocking includes an input data path, a receiver, a set of flip-flops, at least one interpolator and a controller. The receiver is coupled to the input data path for receiving input data. The flip-flops, coupled to the receiver, sample the input data. A fi... | 09/22/2011 |
| 20110176647 | CIRCUIT, SYSTEM AND METHOD FOR MULTIPLEXING SIGNALS WITH REDUCED JITTER An apparatus having a plurality of power supply domains and a plurality of logic components. Each of the plurality of logic components residing within a different one of the plurality of power supply domains. Each of the plurality of logic components is configured to op... | 07/21/2011 |
| 20110170645 | METHOD FOR SWITCHING MASTER/SLAVE TIMING IN A 1000BASE-T LINK WITHOUT TRAFFIC DISRUPTION A method switches master/slave timing in a communication network without traffic disruption. The method includes a master device informing a slave of timing loss. The master device additionally begins transmitting with timing from a local reference clock and begins rece... | 07/14/2011 |
| 20110158367 | DUAL FREQUENCY TRACKING LOOP FOR OFDMA SYSTEMS Methods and apparatus for correcting frequency errors between a carrier frequency of a signal received by a wireless device and a reference frequency local to the device. For certain aspects, such a method generally includes receiving a signal in a receiver having an LO... | 06/30/2011 |
| 20110158368 | LOOP BANDWIDTH ENHANCEMENT TECHNIQUE FOR A DIGITAL PLL AND A HF DIVIDER THAT ENABLES THIS TECHNIQUE A method of operating a phase locked loop (FIG. 5) for a wireless receiver is disclosed. The method includes receiving a reference signal (503) having a first and a second plurality of cycles and receiving a feedback signal (512) having the first an... | 06/30/2011 |
| 20110122983 | FREQUENCY LOCKED FEEDBACK LOOP FOR WIRELESS COMMUNICATIONS A method and systems for a frequency locked feedback loop for wireless communications are provided. The method includes applying dither modulation from a harmonic modulator to modulated data at a transmit source, and mixing the dither modulation at a dither modulation f... | 05/26/2011 |
| 20110116587 | PHASE LOCKED LOOP AND SATELLITE COMMUNICATION TERMINAL USING THE SAME A phase locked loop includes: a loop filter; a voltage controlled oscillating unit configured to output a frequency varying according to an output voltage of the loop filter; a frequency down-converting unit configured to down-convert an output frequency of the voltage ... | 05/19/2011 |
| 20110116586 | Transmitting Apparatus Operative at a Plurality of Different Bands and Associated Method A transmitting apparatus operative at a plurality of different bands includes at least a modulator, an intermediate frequency (IF) filter, and an offset phase-locked-loop (OPLL). Regardless at which one of the frequency bands the transmitting apparatus operates, a divis... | 05/19/2011 |
| 20110110475 | Method and Apparatus to Reduce Wander for Network Timing Reference Distribution A network component comprising a first adaptation component, a second adaptation component, a system Phase-Locked-Loop (PLL) coupled to the first adaptation component, a comparison and voting logic component coupled to the first adaptation component and the system PLL c... | 05/12/2011 |
| 20110103524 | SIGNAL RECEIVING APPARATUS AND SIGNAL TRANSMITTING SYSTEM A signal receiving apparatus 2 has a memory circuit 22, writing of data contained in a digital input signal transmitted from a signal transmitting apparatus 1 is performed using a clock signal separated and created by a PLL circuit 21 from th... | 05/05/2011 |
| 20110090998 | ADC-BASED MIXED-MODE DIGITAL PHASE-LOCKED LOOP A Phase-Locked Loop (PLL) includes a Phase-to-Digital Converter (PDC), a programmable digital loop filter, a Digitally-Controlled Oscillator (DCO), and a loop divider. Within the PDC, phase information is converted into a stream of digital values by a charge pump and an... | 04/21/2011 |
| 20110080985 | Synchronization Distribution in Microwave Backhaul Networks In some embodiments, a system comprises a clock, a root node, a radio channel network, and first and second child nodes. The clock may be configured to generate a clock signal. The root node may be configured to generate a first frame including a first payload and a fir... | 04/07/2011 |
| 20110075782 | STREAM CLOCK RECOVERY IN HIGH DEFINITION MULTIMEDIA DIGITAL SYSTEM The present disclosure provides techniques for recovering source stream clock data at the sink in a high definition multimedia digital content transport system. The disclosure includes a fractional-N Phase-Locked Loop (PLL) based clock generator, a programmable Sigma-De... | 03/31/2011 |
| 20110075781 | CONTINUOUS-RATE CLOCK RECOVERY CIRCUIT A continuous-rate clock and data recovery circuit includes a delay locked loop with a first integrator and a phase locked loop with a separate integrator. The delay locked loop and the phase locked loop are in a dual loop architecture. The first integrator is a digital ... | 03/31/2011 |
| 20110058595 | Method and Apparatus for Detecting In-band Interference in a Data Communications Modem A method and apparatus for detection and analysis of interference and noise in a received signal within a bandwidth of a predetermined communication channel. A receiver receives a modulated signal and generates a demodulated digital baseband signal. A digital quadrature... | 03/10/2011 |
| 20110025913 | CLOCK DATA RECOVERY CIRCUIT AND DISPLAY DEVICE A clock data recovery circuit has: a receiver circuit configured to receive a serial data including a predetermined pattern and to sample the serial data in synchronization with a clock signal to generate a sampled data; a PLL circuit configured to perform clock data re... | 02/03/2011 |
| 20110019718 | Spread Spectrum Clock Generator and Method for Adjusting Spread Amount A spread spectrum clock generator includes a triangular modulator, a delta sigma modulator, a frequency divider, and a phase lock loop. The triangular modulator generates a digital modulation signal, representing a decimal, according to a digital parallel signal, in whi... | 01/27/2011 |
| 20110007859 | PHASE-LOCKED LOOP CIRCUIT AND COMMUNICATION APPARATUS A PLL circuit of which low power consumption and miniaturization are satisfied at the same time is provided. A phase comparator of the PLL circuit includes a counter and a time-to-digital converter. The counter receives a reference clock signal and a low frequency clock... | 01/13/2011 |
| 20100310031 | MULTI-RATE DIGITAL PHASE LOCKED LOOP A Digital Phase-Locked Loop (DPLL) involves a Time-to-Digital Converter (TDC) that receives a DCO output signal and a reference clock and outputs a first stream of digital values. Quantization noise is reduced by clocking the TDC at a high rate. Downsampling circuitry c... | 12/09/2010 |
| 20100303186 | Synchronization circuit, synchronization method, and reception system Disclosed herein is a synchronization circuit including: a first phase-locked loop circuit; a second phase-locked loop circuit; a first output circuit; a second output circuit; a first detection circuit; a second detection circuit; and a control circuit.... | 12/02/2010 |
| 20100303187 | AUTOMATICALLY SYNCHRONIZING RING OSCILLATOR FREQUENCY OF A RECEIVER A ring oscillator in a receiver in a multimedia network is adjusted to compensate for factors that may decrease its accuracy over time using a link training signal from a transmitter device in the network. An incoming signal having a known frequency is received at a rec... | 12/02/2010 |
| 20100296615 | DYNAMIC PHASE TRACKING USING EDGE DETECTION Methods and apparatus of phase tracking are described. Decisions regarding phase location of an oversampled portion of a data signal are based on the content of the data signal. In one example, a phase decision threshold is dynamically variable based on whether a predet... | 11/25/2010 |
| 20100284486 | RECEIVING APPARATUS, TRANSMITTING-RECEIVING APPARATUS, AND TRANSMISSION SYSTEM METHOD THEREFOR A receiving apparatus receives parallel data signals including a plurality of channels from a transmitting apparatus. The receiving apparatus includes a receiver, a detector, and a switch. The receiver receives the parallel data signals. The detector detects a first ske... | 11/11/2010 |
| 20100272222 | PLL MODULATION CIRCUIT, RADIO TRANSMISSION DEVICE, AND RADIO COMMUNICATION DEVICE Provided are a PLL modulation circuit, a radio transmission device, and a radio communication device capable of maintaining a modulation accuracy for modulation of a wide band. The PLL modulation circuit (100) includes: a PLL unit (110), first modulation s... | 10/28/2010 |
| 20100246739 | METHOD FOR MEASURING PHASE LOCKED LOOP BANDWIDTH PARAMETERS FOR HIGH-SPEED SERIAL LINKS A method for measuring a phase locked loop bandwidth parameter for a high-speed serial link includes the steps of initiating a jitter frequency of a clock input of a phase locked loop equal to a reference frequency with a frequency generator, determining a reference jit... | 09/30/2010 |
| 20100208857 | PHASE-LOCKED LOOP CIRCUIT AND RELATED PHASE LOCKING METHOD A phase-locked loop circuit, including: an operating circuit for detecting a difference between a reference signal and a feedback oscillating signal to generate a detected result, and generating a first control signal according to the detected result, an auxiliary circu... | 08/19/2010 |
