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| Application No. | Application Title | Issue Date |
| 20100322367 | Fast Phase Alignment for Clock and Data Recovery Disclosed herein are systems and methods for fast phase alignment and clock and data recovery. Systems and methods may include a fast phase alignment component configured to generate a selected phase signal based on a characteristic of an incoming signal. A clock and da... | 12/23/2010 |
| 20100158182 | Method and System for Reducing Duty Cycle Distortion Amplification in Forwarded Clocks A method and apparatus for reducing the amplification of the duty cycle distortion of high frequency clock signals when is provided. A data signal is sent to a receiver via a first channel. A clock signal is sent to the receiver via a second channel. The clock signal is... | 06/24/2010 |
| 20100067633 | FAST POWERING-UP OF DATA COMMUNICATION SYSTEM A data communication system has a transmitter with a first clock-generation circuit, and a receiver with a second clock generation circuit. At least a specific one of the clock-generation circuits is powered-down between consecutive data bursts. The system expedites the... | 03/18/2010 |
| 20100040184 | METHOD AND SYSTEM FOR COEXISTENCE IN A MULTIBAND, MULTISTANDARD COMMUNICATION SYSTEM UTILIZING A PLURALITY OF PHASE LOCKED LOOPS Methods and systems for coexistence in a multiband, multistandard communication system utilizing a plurality of phase locked loops (PLLs) are disclosed. Aspects may include determining one or more desired frequencies of operation of a transceiver, determining a frequenc... | 02/18/2010 |
| 20090316847 | Automatic Synchronization of an Internal Oscillator to an External Frequency Reference An internal integrated circuit clock oscillator is automatically synchronized to an external frequency reference by counting the number of periods of the internal clock oscillator (hereinafter “count”) that occur within a period of a lower frequency external frequen... | 12/24/2009 |
| 20090310667 | PHASE CONTROL BLOCK FOR MANAGING MULTIPLE CLOCK DOMAINS IN SYSTEMS WITH FREQUENCY OFFSETS A circuit for performing clock recovery according to a received digital signal (30). The circuit includes at least an edge sampler (105) and a data sampler (145) for sampling the digital signal, and a clock signal supply circuit. The clock signal su... | 12/17/2009 |
| 20090279655 | FAST LOCKING CLOCK AND DATA RECOVERY A clock data recovery comprises a phase detector, a phase interpolator, an initial phase detector, and an initial phase decoder. The phase detector receives an incoming data stream and an interpolated clock signal and output an early/late value indicating timing relatio... | 11/12/2009 |
| 20090262876 | PHASE COMPARATOR AND REGULATION CIRCUIT A phase comparison process in a timing recovery process for high-speed data communication defines a data window and compares the phase of a clock in the window with the phase of an edge of data so as to realize a parallel process, wherein the phase comparison and the pr... | 10/22/2009 |
| 20090262875 | Communication apparatus A conventional apparatus has a problem that delay occurs in selection of the phase of a synchronization clock. A communication apparatus according to the present invention includes: a first unit 21 which performs sampling of a synchronization pattern included in ... | 10/22/2009 |
| 20090245448 | Adaptation of a digital receiver A method and apparatus to improve adaptation speed of a digital receiver is presented. The receiver includes an equalizer to initiate adaptation to a transmission channel responsive to a first control signal, a slicer coupled to the equalizer to generate symbol decision... | 10/01/2009 |
| 20090190643 | CARRIER PHASE INDEPENDENT SYMBOL TIMING RECOVERY METHODS FOR VSB RECEIVERS The present invention provides a novel symbol timing recovery method for VSB receivers. Systems are described that comprise a timing error detector (TED) that produces an exact symbol timing error even in the presence residual carrier phase offset, loop filter that cont... | 07/30/2009 |
| 20090168942 | Apparatus and method for frequency synthesis using delay locked loop An apparatus and method for frequency synthesis using a Delay Locked Loop (DLL) are provided. The apparatus includes the DLL, an edge pulse generator, and an inductive-capacitive (LC) tank switch. If phases of a reference frequency signal and a feedback signal are the s... | 07/02/2009 |
| 20090168943 | CLOCK GENERATION DEVICES AND METHODS A clock generation device provided for a transmitter is provided and comprises a clock generator, a calculator and a first phase locked loop (PLL) circuit. The clock generator generates a first clock signal. The calculator calculates a frequency difference between the f... | 07/02/2009 |
| 20090154619 | FREQUENCY ERROR ESTIMATOR USING SECOND-ORDER LOOP FILTER AND OPERATING METHOD OF THE FREQUENCY ERROR ESTIMATOR A frequency error estimator and an operating method of the frequency error estimator are provided. In the frequency error estimator and the operating method of the frequency error estimator, a frequency error between a transmitter and a receiver of a mobile communicatio... | 06/18/2009 |
| 20090147827 | Methods, Systems, and Computer Program Products for Implementing Spread Spectrum Using Digital Signal Processing Techniques Implementing spread spectrum using digital signal processing techniques. An incoming clock signal is received and sampled using a programmable sampling mechanism to generate a plurality of signal data points included in a sampled signal. The sampled signal is conditione... | 06/11/2009 |
| 20090129514 | Accurate data-aided frequency tracking circuit A frequency compensation circuit for compensating for a frequency offset in a received signal, the received signal including a periodically repeated pilot sequence for phase locking. The circuit comprises a phase estimator for estimating a phase of the received signal; ... | 05/21/2009 |
| 20090097608 | PHASE DETECTING CIRCUIT AND CLOCK GENERATING APPARATUS INCLUDING THE SAME A phase detecting circuit includes a first node that outputs a pull-up control signal, a second node that outputs a pull-down control signal, an initializing unit that initializes voltage levels of the first and second nodes in response to a pre-charge signal, a data in... | 04/16/2009 |
| 20090097605 | SYSTEM FOR PHASE OFFSET CANCELLATION IN SYSTEMS USING MULTI-PHASE CLOCKS A system for use with a multi-phase clock generator is disclosed. It should also be understood that the multiphase clock generator can be a phase lock loop (PLL), delay lock loop (DLL), or any other circuit capable of providing a multiphase clock. The system comprises a... | 04/16/2009 |
| 20090074127 | PHASE LOCKING METHOD AND APPARATUS A phase locking method and apparatus by which a phase of an input signal is locked using the input signal and a clock signal, where the phase locking method includes generating n multi-phase clock signals using the clock signal where n is an integer, generating n multi-... | 03/19/2009 |
| 20090046822 | System and Method for Clock Drift Compensation Embodiments for compensating clock drift in a system have been described and depicted.... | 02/19/2009 |
| 20080285696 | Techniques for integrated circuit clock management using multiple clock generators A clock generator system (400) includes a phase locked loop (PLI,) (402), a first clock generator (404), and a second clock generator (406). The PLL (402) includes a first output configured to provide a first clock signal at a first fr... | 11/20/2008 |
| 20080260086 | CARRIER SYNCHRONIZING CIRCUIT AND CARRIER SYNCHRONIZING METHOD Disclosed herein is a carrier synchronizing circuit including at least frequency synchronizing means and phase synchronizing means. The phase synchronizing means includes residual frequency error detecting means for detecting a residual frequency error after a frequency... | 10/23/2008 |
| 20080175343 | Phase adjusting function evaluating method, transmission margin measuring method, information processing apparatus, program and computer readable information recording medium A phase amount added to a clock signal or a plurality of data signals for adjusting a phase relationship therebetween in a reception apparatus is changed, and, a result of the phase adjusting operation is stored when the phase amount added to the clock signal or the plu... | 07/24/2008 |
| 20080170651 | Correction of mismatches between two I and Q channels A method for correcting mismatches between a digital signal in phase and a digital signal in quadrature originating from a signal broadcast by terrestrial channel, comprising a phase correction method. A set of first error values is measured during a first period. A cur... | 07/17/2008 |
| 20080159460 | ADJUSTMENT METHOD, CIRCUIT, RECEIVER CIRCUIT AND TRANSMISSION EQUIPMENT OF WAVEFORM EQUALIZATION COEFFICIENT In an adjustment method of waveform equalization coefficient, one of jitter and amplitude is measured only in a case of an arbitrary signal sequence and a waveform equalization coefficient is adjusted. Particularly, using a signal of received signals other than a 010 si... | 07/03/2008 |
| 20080152065 | AUTOMATIC FREQUENCY MONITORING CIRCUIT, ELECTRONIC DEVICE, AUTOMATIC FREQUENCY MONITORING METHOD, AND AUTOMATIC FREQUENCY MONITORING PROGRAM An automatic frequency monitoring circuit automatically monitors a frequency of a clock related to an operation of a device to be monitored. In the automatic frequency monitoring circuit, a frequency detecting unit detects, upon detecting a predetermined momentum, the f... | 06/26/2008 |
| 20080130816 | Serializer deserializer circuits A phase lockedcircuit comprising a phase detector for comparing an incoming serial data signal with a feedback clock signal and generating a digital phase detector output signal representing a phase difference between the incoming data signal and the feedback clock sign... | 06/05/2008 |
| 20080130815 | Selective tracking of serial communication link data Embodiments to selectively track serial communication link data are presented herein.... | 06/05/2008 |
| 20080095291 | Clock data recovery systems and methods for direct digital synthesizers A system and method for clock data recovery for programming direct digital synthesizers is disclosed. A counter is used to calculate a coarse measurement of the clock frequency of a received digital signal, and a tap delay line is used to calculate a fine measurement of... | 04/24/2008 |
| 20080095292 | APPARATUS AND METHOD FOR CLOCK PHASE ALIGNMENT BETWEEN ACTIVE AND STANDBY CLOCK CARDS AND CLOCK CARD The present invention discloses an apparatus and a method for clock phase alignment between active and standby clock cards. The apparatus includes: a Direct Digital Synthesizer (DDS) adapted for adjusting a clock phase of a clock card; a phase detection module adapted f... | 04/24/2008 |
| 20080080649 | Method and apparatus for clock skew calibration in a clock and data recovery system using multiphase sampling Methods and apparatus are provided for clock skew calibration in a clock and data recovery system. One aspect of the invention compensates for skew among a plurality of clocks in a clock and data recovery system. The clocks are applied to a plurality of latches to sampl... | 04/03/2008 |
| 20080069282 | Jitter suppression circuit In a circuit suppressing jitters without a synchronizing clock signal and an increase of a circuit scale, input data is regenerated by a data regeneration circuit in a broadband, a predetermined signal pattern which generates phase deviations exceeding a predetermined v... | 03/20/2008 |
| 20080056426 | Clock and Data Recovery A data and clock recovery circuit having a retimer mode and a resync mode. In one embodiment, a receiver circuit includes: a retimer; a clock recovery circuit to provide a clock signal to the retimer; and an adjustable delay to provide a delayed version of an input sign... | 03/06/2008 |
| 20080025453 | SAMPLING-ERROR PHASE COMPENSATING APPARATUS AND METHOD THEREOF A sampling-error phase compensating device and a method thereof for sequentially sampling data signals and outputting sampled data signals. The method sequentially includes the steps of: sampling each data signal according to a first sampling clock signal, and sequentia... | 01/31/2008 |
| 20080013664 | PHASE ERROR MEASUREMENT CIRCUIT AND METHOD THEREOF A phase error measurement circuit and related method, and in particular a recyclable phase error measurement circuit and related method applied in a phase detector for calculating a phase error value is disclosed. A phase error measurement circuit for calculating a phas... | 01/17/2008 |
| 20070297553 | Clock offset compensator A device comprises a transmitter, a receiver and a clock generator that generates a local clock frequency. A clock recovery circuit communicates with the receiver and recovers a host clock frequency from data received from a host by the receiver. A frequency offset circ... | 12/27/2007 |
| 20070291888 | System and method for an adaptable timing recovery architecture for critically-timed transport applications The present invention provides a timing recovery architecture and circuit for recovering the clock timing from a received signal in critically-timed transport applications. The present invention further relates to a timing recovery architecture and circuit for removing ... | 12/20/2007 |
| 20070263756 | MOBILE COMMUNICATION TERMINAL HAVING CLOCK CONTROL FUNCTION AND CLOCK CONTROL METHOD FOR THE SAME A mobile communication terminal having a clock control function and a clock control method for the same are provided. The terminal includes a first oscillator configured to produce a first clock having a frequency which is not affected by interference from a specific ch... | 11/15/2007 |
| 20070253517 | Method and apparatus for integral state initialization and quality of lock monitoring in a clock and data recovery system Methods and apparatus are provided for improving the performance of second order CDR systems. The integral state of the CDR system is initialized to a value that is based on an expected frequency profile that may be known a priori for certain applications. One or more q... | 11/01/2007 |
| 20070230649 | Impulse noise detection from preamble symbols A communication device constructed according to the present invention detects impulse noise in a preamble sequence. In detecting impulse noise in the preamble sequence the communication device first receive a preamble sequence that includes a plurality of preamble symbo... | 10/04/2007 |
