Class 375/372 - Elastic buffer

Subclass of Class 375 - Pulse or digital communications
Definition: Subject matter wherein a first in-first out (FIFO) storage
No. of applications: 63
Last issue date: 07/01/2010

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Application No.	Application Title	Issue Date
20100166132	PLL/DLL DUAL LOOP DATA SYNCHRONIZATION A dual loop (PLL/DLL) data synchronization system and method for plesiochronous systems is provided. A dual loop data serializer includes a phase lock loop (PLL) and a delayed lock loop (DLL) configured with a phase shifter in the feedback path of the PLL. The dual loop...	07/01/2010
20100054385	ADAPTIVE ELASTIC BUFFER FOR COMMUNICATIONS Circuit and method for an adaptive elastic buffer for receiving data including timing signals. Received data is recovered and stored in the adaptive elastic buffer, and a recovery clock pointer is increased to identify the next buffer location for stuffing received data...	03/04/2010
20100020912	CLOCK SYNCHRONISER A clock synchroniser, for generating a local clock signal synchronised to a received clock signal, is described and claimed, along with a corresponding clock synchronisation method. The clock synchroniser incorporates a reference oscillator providing a reference signal,...	01/28/2010
20090296868	Method for Shifting Data Bits Multiple Times Per Clock Cycle A system and method are used to allow for phase rotator control signals to be produced that rotate bits in the signals more than one step per clock cycle. This can be done through the following operation. First and second data signals that include a plurality of data bi...	12/03/2009
20090290596	METHOD AND APPARATUS FOR GENERATING VIRTUAL CLOCK SIGNALS The invention includes a method and apparatus for generating virtual clock signals for differing hierarchies in a communication system conveying data frames of differing hierarchies. Specifically, a method according to one embodiment of the invention includes receiving ...	11/26/2009
20090232266	SIGNAL PROCESSING DEVICE A signal processing device includes a phase shifting unit for supplying a second clock signal having a predetermined phase difference relative to a first clock signal, a head recognition bit adding unit for adding a head recognition bit to a predetermined position of da...	09/17/2009
20090141844	Methods and apparatus for interface buffer management and clock compensation in data transfers A circuit for data stream buffer management, lane alignment, and clock compensation of data transfers across a clock boundary using a single first in first out (FIFO) buffer in each serial channel is described. The RapidIO® data channel, for example, operates using a c...	06/04/2009
20090116602	High speed, wide frequency-range, digital phase mixer and methods of operation The present disclosure is directed to a unit phase mixer in combination with an input buffer. The unit phase mixer has a pull-up path for pulling an output terminal up to a first voltage. The pull-up path has a first transistor responsive to a first enable signal and a ...	05/07/2009
20090086874	Apparatus and method of elastic buffer control A method, system, and apparatus for synchronizing an asynchronous data transmission between a transmitter and a receiver are presented. For example, an elastic buffer can include a symbol storage coupled to receive transition data from a transmitter and to store the tra...	04/02/2009
20090052601	METHOD AND APPARATUS FOR FRAME-BASED BUFFER CONTROL IN A COMMUNICATION SYSTEM A method and apparatus are disclosed for controlling a buffer in a digital audio broadcasting (DAB) communication system. The decoder buffer level limits are specified in terms of a maximum number of encoded frames (or duration). The transmitter can predict the number o...	02/26/2009
20080267333	Method And Apparatus For Controlling Buffer Overflow In A Communication System A method and apparatus are disclosed for controlling a buffer in a digital audio broadcasting (DAB) communication system. An audio encoder marks a frame as “dropped” whenever a buffer overflow might occur. Only a small number of bits are utilized to process a lost f...	10/30/2008
20080256300	System and method for dynamically reconfiguring a vertex cache A system to process a plurality of vertices to model an object. An embodiment of the system includes a processor, a front end unit coupled to the processor, and cache configuration logic coupled to the front end unit and the processor. The processor is configured to pro...	10/16/2008
20080240326	HIGH SPEED DIGITAL WAVEFORM IDENTIFICATION USING HIGHER ORDER STATISTICAL SIGNAL PROCESSING In some embodiments an apparatus includes a higher order statistical signal processor to process a jittered digital signal, a diagonal line average unit to identify a distinct line in a signal output from the higher order statistical signal processor, and a peak detecti...	10/02/2008
20080187085	Method and Apparatus for the Capture of Serial Data Amid Jitter Serial data in the presence of jitter is captured by clocking the data into several different shift registers, each driven by a clock of the correct frequency but having different phases. In keeping with certain system standards, a periodic synchronization frame is tran...	08/07/2008
20080130814	MULTI-LANE ELASTIC BUFFER CLUSTER FOR CLOCK TOLERANCE COMPENSATION AND DE-SKEW AMONG MULTIPLE RECEIVING LANES System and method for data transfer with buffer control. According to an embodiment, the present invention provides a system for synchronized data communication. The system includes a first communication interface for receiving data and a first clock signal. For example...	06/05/2008
20080112523	DATA SYNCHRONIZATION APPARATUS A data synchronization apparatus is provided. The data synchronization apparatus comprises a first-in first-out buffer (FIFO buffer), a control circuit and a phase-locked loop (PLL). The FIFO buffer receives and stores a plurality of data and provides a FIFO adjustment ...	05/15/2008
20080101522	Programmable Local Clock Buffer A programmable clock generator circuit receives control signals and a global clock and generates a pulsed data clock and a scan clock in response to gating signals. The clock generator has data clock and scan clock feed-forward paths and a single feedback path. Delay co...	05/01/2008
20080075219	Rate adaptation A method and system for providing single stage pointer and overhead processing is disclosed. In accordance with one embodiment of the invention, data including bytes of each of multiple types of overhead data is received at a logical element of a communications network....	03/27/2008
20080056341	Finding Low Frequency Random and Periodic Jitter in High Speed Digital Signals Simultaneously measurements of jitter in a high speed signal expected to exhibit both short and long period jitter are made even when the amount of acquisition memory is fixed and cannot be increased to allow storage of consecutive uninterrupted high speed samples for t...	03/06/2008
20080049795	Jitter buffer adjustment For enhancing the performance of an adaptive jitter buffer, a desired amount of adjustment of a jitter buffer is determined at a first device using as a parameter an estimated delay. The delay comprises at least an end-to-end delay in at least one direction in a convers...	02/28/2008
20080013663	Signal buffering and retiming circuit for multiple memories A signal buffering and retiming (SBR) circuit for a plurality of memory devices. A PLL-based clock generator generates a set of phase-shifted clock signals from a received host clock signal. Each of a plurality of phase selectors independently selects a subset of contig...	01/17/2008
20070291888	System and method for an adaptable timing recovery architecture for critically-timed transport applications The present invention provides a timing recovery architecture and circuit for recovering the clock timing from a received signal in critically-timed transport applications. The present invention further relates to a timing recovery architecture and circuit for removing ...	12/20/2007
20070280396	Method and system for advance high performance bus synchronizer Provided is a method for transferring data from one clock domain within a synchronizer to another domain within the synchronizer. The method includes determining system clock parameters within the synchronizer and analyzing a first domain clock signal based upon the sys...	12/06/2007
20070263755	Method of transmitting time information with fixed latency The invention relates to a method of transmitting time information relating to the clock of the source of a sending part consisting in using a fixed latency indicator signal to authorize the source to insert time information used to slave the clock of the decoder of the...	11/15/2007
20070201592	Multi-channel fractional clock data transfer Methods and apparatus to transfer data between one or more clock domains are described. In one embodiment, a signal corresponding to a read pointer of a buffer is generated in response to a plurality of signals that correspond to write pointers of the buffer. ...	08/30/2007
20070201593	Egress pointer smoother A method and apparatus that allows egress pointer smoothing data by evaluating the average fill of an elastic store. For one embodiment of the invention, by measuring the average fill, the 3 bytes of SOH and 87 bytes of data are taken together in each sample, and the re...	08/30/2007
20070183551	Method and circuit for obtaining asynchronous demapping clock A method and a circuit for obtaining asynchronous demapping clock. The method includes: obtaining a smoothed clock with even gaps in accordance with data to be demapped and a corresponding clock signal; performing phase locking in accordance with a signal reflecting wri...	08/09/2007
20070177701	Receiver and method for synchronizing and aligning serial streams A receiver for receiving a stream of symbols clocked at a first rate, and providing the symbols at a second clock rate uses two buffers. Incoming symbols are written to a first dual clock buffer at the first rate, and read from the first and second buffer, at the second...	08/02/2007
20070172011	Sampling rate mismatch solution Methods and apparatuses for compensating for differences in communication system transmit and receive clock signal frequencies include buffer timing modification and sample addition. In buffer timing modification, a buffer clock signal is interrupted as needed to slow t...	07/26/2007
20070165761	Method and system for universal sampling rate conversion A sampling rate converter (100) is provided. The system can include a data buffer (102), a processor (104) for processing data in the buffer (10), and a plurality of sampling rate lines for configuring the processor. For example, the input si...	07/19/2007
20070165762	NICAM audio signal resampler A NICAM audio signal re-sampler may include a non-linear interpolator configured to interpolate in a non-linear manner between sequential digital samples that are based on a stream of demodulated NICAM audio samples. A phase differential calculator may be included that ...	07/19/2007
20070165763	System and method for transporting unaltered optical data stream Embodiments of the invention provide systems, apparatuses, and methods for maintaining proper bit sequence as well as the rate at which the bits occur within the data stream, enabling the transport of an unaltered optical stream from one point to another. Bits of data i...	07/19/2007
20070140398	Data receiving device and data receiving method A receiving device (50) is provided to allow appropriate clock regeneration even for a VBR TS when a stream including video and audio data, such as an MPEG2 TS, is transmitted or received in real time through a network having jitter. When the received packet data...	06/21/2007
20070086554	Data synchronizer and data synchronizing method According to an embodiment of the present invention, a data synchronizer for outputting data with a readout clock frequency sync with input data or receiving data with a read-in clock frequency sync with output data, includes: a frequency synchronizer controlling a freq...	04/19/2007
20070064853	TECHNIQUES TO REDUCE TRANSMITTED JITTER A re-timer system that may include a phase recoverer (“PR”), first-in-first-out device (“FIFO”) and retime clock multiplication unit (“CMU”). PR may receive an input signal that suffers from jitter. PR may generate a phase matched signal having substantially...	03/22/2007
20070058766	Methods and apparatus for recovering serial data A phase alignment device for alignment of phase between a data signal and a clock signal is described. The phase alignment device includes a signal generator generating an enable signal configured to control shifting of the data signal through an external data buffering...	03/15/2007
20070047685	Semiconductor device An improved reception port for receiving packet data based on the IEEE 1394 standard. The reception port includes a synchronization FIFO memory for receiving reception data in accordance with a reception clock signal and synchronizing the reception data with an internal...	03/01/2007
20070025487	Clock transferring apparatus, and testing apparatus There is provided a clock transferring apparatus for synchronizing a pattern signal synchronized with a reference clock with a variable clock based on an oscillation source different from that of the reference clock, having a rate clock generating section for generating...	02/01/2007
20070025488	RAM-DAC for transmit preemphasis Described are transmitters with RAM-DAC based pre-emphasis filters that can be updated adaptively without interfering with data transmission. The memory within the RAM-DAC is divided into active and inactive memory locations, in which active memory locations are those t...	02/01/2007
20070019771	Communication protocol for networked devices A communication protocol in a wireless network of a transceiver and a plurality of devices, in which at least one device is a bidirectional device, and in which one or more other devices can be unidirectional devices. The unidirectional device communicates with the tran...	01/25/2007

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Class 375/372 - Elastic buffer