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| Application No. | Application Title | Issue Date |
| 20120128110 | METHOD AND SYSTEM FOR ELIMINATING IMPLEMENTATION TIMING IN SYNCHRONIZATION CIRCUITS A method and system for eliminating implementation timing with respect to a synchronization circuit. A standard library cell having a pair of dock input pins can be connected with at least two asynchronous dock domains of the synchronization circuit in order to measure ... | 05/24/2012 |
| 20120106687 | Calibration of Multiple Parallel Data Communications Lines for High Skew Conditions A parallel data link includes a redundant line. A bank of switches permits any arbitrary line of the link to be enabled or disabled for carrying functional data, each line being dynamically calibrated in turn by disabling the line and allowing other lines to carry the f... | 05/03/2012 |
| 20120082279 | PLURAL CIRCUIT SELECTION USING ROLE REVERSING CONTROL INPUTS Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and mode inputs. The data communication circuits have data inputs, data outputs, a clock input for timing or synchron... | 04/05/2012 |
| 20120027135 | SYSTEM AND METHOD FOR SYNCHRONIZATION TRACKING IN AN IN-BAND MODEM Processing the synchronization of an inband modem to detect sample slip conditions is disclosed. Decision logic reliably detects the sample slip condition while minimizing the number of false alarms.... | 02/02/2012 |
| 20120027144 | MULTI-PHASE CLOCK SWITCHING DEVICE AND METHOD THEREOF A multi-phase clock switching device includes a plurality of phase selection circuits. The phase selection circuit is used to receive a plurality of phase clock signals and determine how to output the phase clock signals to generate an output signal according to a switc... | 02/02/2012 |
| 20120027143 | CLOCK GENERATOR FOR GENERATING OUTPUT CLOCK HAVING NON-HARMONIC RELATIONSHIP WITH INPUT CLOCK AND RELATED CLOCK GENERATING METHOD THEREOF One clock generator includes an oscillator block, a delay circuit, and an output block. The oscillator block provides a first clock of multiple phases. The delay circuit delays at least one of said multiple phases of said first clock to generate a second clock of multip... | 02/02/2012 |
| 20120020404 | CLOCK-SYNCHRONIZED METHOD FOR UNIVERSAL SERIAL BUS (USB) A clock-synchronized method for universal serial bus (USB) is described. The method includes the following steps of: (a) a transmitter sends a periodic signal to a host unit during a first time interval; (b) the host unit transmits a first equalization training sequence... | 01/26/2012 |
| 20120020417 | Method for Accurate Distribution of Time to a Receiver Node in an Access Network An apparatus comprising a customer node configured to couple to an access node and to receive via a channel from the access node a time of day (TOD) value and a corresponding sample index (SNUM) value, wherein the TOD value and the SNUM value are used to estimate a seco... | 01/26/2012 |
| 20120014490 | REAL TIME DISTRIBUTED EMBEDDED OSCILLATOR OPERATING FREQUENCY MONITORING A method for clock monitoring in a network is provided. The method comprises receiving a first network clock signal at a network device and comparing the first network clock signal to a local clock signal from a primary oscillator coupled to the network device.... | 01/19/2012 |
| 20120002771 | RECEIVER, SEMICONDUCTOR DEVICE, AND SIGNAL TRANSMISSION METHOD A receiver comprises: a reception coil through which flow a current of a polarity corresponding to data is allowed to flow by flowing a current through a transmission coil for every rising edge or falling edge of a clock signal relating to transmission of data, and gene... | 01/05/2012 |
| 20110311009 | PATTERN AGNOSTIC ON-DIE SCOPE An on-die scope is described. The on-die scope can include one or more scope slicers, phase sweeping circuitry, voltage sweeping circuitry, and eye-diagram data collection circuitry. The clock and data recovery circuitry can receive an input signal, and output a recover... | 12/22/2011 |
| 20110299642 | NOISE SHAPED INTERPOLATOR AND DECIMATOR APPARATUS AND METHOD Improved interpolator and decimator apparatus and methods, including the addition of an elastic storage element in the signal path. In one exemplary embodiment, the elastic element comprises a FIFO which advantageously allows short term variation in sample clocks to be ... | 12/08/2011 |
| 20110280353 | Adaptive phase-shifted synchronization clock generation circuit and method for generating phase-shifted synchronization clock The present invention discloses an adaptive phase-shifted synchronization clock generation circuit and a method for generating phase-shifted synchronization clock. The adaptive phase-shifted synchronization clock generation circuit includes: a current source generating ... | 11/17/2011 |
| 20110280354 | FRAME TIMING CONTROLLER AND FRAME TIMING CONTROL METHOD FOR TRIGGERING AT LEAST RECEIVER IN MOBILE STATION TO START RECEIVING TRANSMITTED INFORMATION OF BASE STATION BY REFERRING TO AT LEAST FRAME POINTER A frame timing controller includes a timer, a frame timing control unit, and a frame pointer processing circuit. The timer is arranged to generate a timer value according to a first clock signal with a first clock frequency. The frame timing control unit is for triggeri... | 11/17/2011 |
| 20110274226 | SYNCHRONIZATION PROCESSING CIRCUIT AND SYNCHRONIZATION PROCESSING METHOD IN WIRELESS COMMUNICATION SYSTEM In a synchronization processing circuit in a wireless communication system, a correlation operation unit is designed to have a parallel structure which can be restructured to improve flexibility in order to cope with various synchronization processings in a plurality of... | 11/10/2011 |
| 20110268234 | METHOD AND APPARATUS FOR TRANSMITTING AND RECEIVING A TIMING CORRECTION MESSAGE IN A WIRELESS COMMUNICATION SYSTEM A method for transmitting a timing correction message in a wireless communication system, the method comprising, Generating the timing correction message comprising a 8-bit MessageID field and a 2-bit NumSectors field wherein, the NumSectors field indicates the number o... | 11/03/2011 |
| 20110268233 | APPARATUS AND METHOD FOR TIMING OF SIGNALS The invention relates to a method and an apparatus (1) for the timing of signals (2), preferably of signals (2) including fast changing disturbances, the apparatus (1) comprising a first timer (3) and a second timer (4), the fir... | 11/03/2011 |
| 20110261914 | Digital Modulator The present application relates to a digital modulator comprising an output stage comprising a number of unit cell arrays, and a sampling stage. The present application relates also to a communication device comprising said digital modulator, a method for digitally modu... | 10/27/2011 |
| 20110249780 | OFDM Frame Synchronisation Method and System An OFDM frame synchronisation method in which the symbols of the preamble carry a code. The detection of the code allows the frame synchronization in presence of low SNR.... | 10/13/2011 |
| 20110249781 | DEVICE FOR RECONSTRUCTING THE CLOCK OF AN NRZ SIGNAL, AND ASSOCIATED TRANSMISSION SYSTEM The invention relates according to a first aspect to a device (1) for reconstructing a clock signal from a baseband serial signal (NRZ-D), comprising:-a pulse generating circuit (2) adapted for generating pulses at each transition, rising or falling, of th... | 10/13/2011 |
| 20110235762 | SYMBOL TIMING SYNCHRONIZATION METHODS AND APPARATUS Embodiments include methods and apparatus for performing symbol timing synchronization for a symbol-bearing signal. The symbol-bearing signal is sampled to produce a plurality of symbol samples. First-direction interpolation processes are performed on the plurality of s... | 09/29/2011 |
| 20110228885 | TIME SYNCHRONIZATION SYSTEM VIA TWO-WAY INTERACTIVE WIRELESS COMMUNICATION The time synchronization system according to the present invention can allow the master and slave time Tx/Rx devices to communicate information therebetween via two-way interactive wireless communication, so that it can rapidly detect an error that occurs in the system,... | 09/22/2011 |
| 20110216861 | CIRCUITRY SYSTEM AND METHOD FOR CONNECTING SYNCHRONOUS CLOCK DOMAINS OF THE CIRCUITRY SYSTEM A clock domain separation device and a method for operating the device is provided for separating two clock domains of a bus system in a system-on-chip (SoC). The clock domain separation device is a hardware module that acts as a guarding between the two clock domains t... | 09/08/2011 |
| 20110216860 | COMMUNICATION METHOD A communication method is provided to reduce an overhead of inter-processor synchronization for a communication phase in collective communication and to speed up the collective communication. Each of processors in a parallel computer start a previous process before a co... | 09/08/2011 |
| 20110206172 | COARSE TIME SYNCHRONIZATION A system for determining the burst start timing of a signal includes logic configured to receive the signal, generate correlation moduli and generate a first timing output based on the correlation moduli. The logic may also be configured to receive operating mode inform... | 08/25/2011 |
| 20110193742 | Method and Apparatus for Weak Data Frame Sync in a Positioning System The present invention is related to location positioning systems, and more particularly, to a method and apparatus of synchronizing to data frames in a positioning system signal. According to one aspect, the invention speeds up the frame synchronization process by compu... | 08/11/2011 |
| 20110188619 | Electronic circuit, electronic apparatus, and digital signal processing method A local timing circuit receives a reference timing signal and generates a multi-phase timing signal for output to a digital signal processing circuit.... | 08/04/2011 |
| 20110188620 | Method and Apparatus for Providing a Synthetic System A method and apparatus of providing a configurable computer system capable of being modeled are disclosed. The system, in one embodiment, includes a configurable component and a clock distributor. The configurable component includes multiple programmable devices arrange... | 08/04/2011 |
| 20110188621 | CLOCK AND DATA RECOVERY CIRCUITRY WITH AUTO-SPEED NEGOTIATION AND OTHER POSSIBLE FEATURES An integrated circuit (“IC”) may include clock and data recovery (“CDR”) circuitry for recovering data information from an input serial data signal. The CDR circuitry may include a reference clock loop and a data loop. A retimed (recovered) data signal output by... | 08/04/2011 |
| 20110176589 | METHODS AND SYSTEMS FOR MEASURING DATA PULSES Some embodiments disclosed herein relate to a method. In the method, a duration of a first synchronization pulse is measured. A fixed, predetermined number of ticks are equally spaced at a first time interval over the first sync pulse, regardless of the duration of the ... | 07/21/2011 |
| 20110176646 | METHOD AND SYSTEM FOR DETERMINING BIT STREAM ZONE STATISTICS An input bit stream is received and zone statistics such as zones count, zones center bit positions, and zones lengths are determined, where a zone is a set of non-transitioning bits in the input bit stream. Beginning and ending bit positions for each zone are determine... | 07/21/2011 |
| 20110170645 | METHOD FOR SWITCHING MASTER/SLAVE TIMING IN A 1000BASE-T LINK WITHOUT TRAFFIC DISRUPTION A method switches master/slave timing in a communication network without traffic disruption. The method includes a master device informing a slave of timing loss. The master device additionally begins transmitting with timing from a local reference clock and begins rece... | 07/14/2011 |
| 20110164710 | TRANSMISSION TIMING ADJUSTMENT IN RADIO SYSTEMS A method of adjusting the transmission time of a signal in a radio link, the method being performed by a transmitter configured to transmit the signal over the radio link to a receiver and comprising the steps of ascertaining an accuracy that the receiver assumes for th... | 07/07/2011 |
| 20110150156 | METHOD FOR GENERATING A PREAMBLE SEQUENCE AND A METHOD FOR DETERMINING A CYCLIC SHIFT A method for generating a preamble sequence and determining a cyclic shift. The method includes: when set a piece of root sequence can only generate one preamble sequence and there is no cyclic shift restriction, setting the cyclic shift step length NCS to be... | 06/23/2011 |
| 20110150481 | ELECTRICAL RETURN-TO-ZERO (ERZ) DRIVER CIRCUIT Consistent with the present disclosure, clock-and-data recovery (CDR) circuitry and driver circuitry are provided on a chip that is separate from the driver circuitry, thereby reducing the amount of power consumed by the driver circuitry and simplifying system design. I... | 06/23/2011 |
| 20110135046 | INTEGRATED CIRCUIT PACKAGE WITH MULTIPLE DIES AND A SYNCHRONIZER A package includes a first die and a second die. The dies are connected to each other through an interface. The interface is configured to transport both control signals and memory transactions. A synchronizer is provided on at least one of said first and second of said... | 06/09/2011 |
| 20110122978 | SERIAL PERIPHERAL INTERFACE HAVING A REDUCED NUMBER OF CONNECTING LINES An electronic communication system including at least one first communication unit and one second communication unit which are connected to one another by means of at least one first data line. The communication system has a data transmission protocol according to which... | 05/26/2011 |
| 20110122929 | Serialization of multi-band sequence keying for ultra wideband receiver architecture with reduced complexity and power consumption By partially serializing the transmission of a sequence keyed UWB symbol (FIG. 2), the number of parallel receiver branches required to receive such a transmission is reduced. The reduced number of receiver paths are re-used during the reception of each of the pa... | 05/26/2011 |
| 20110103456 | METHOD AND SYSTEM FOR LOW COMPLEXITY CONJUGATE GRADIENT BASED EQUALIZATION IN A WIRELESS SYSTEM A method for processing signals includes, in a wireless system comprising one or more processors and/or circuits integrated within a single chip, initializing values related to at least one channel response vector and at least one correlation vector using a conjugate gr... | 05/05/2011 |
| 20110096880 | Lossless Transfer Of Events Across Clock Domains Transfer circuits (200, 400, 500) for monitoring in a monitor clock domain target events that occur in a target clock domain (170) are disclosed. Some embodiments (200) impose significant constraints on the domain clocks and include: an event detect... | 04/28/2011 |
